FemtoClock™ Dual VCXO Video PLL
810001-22
DATA SHEET
General Description
The 810001-22 is a PLL based synchronous clock generator that is
optimized for digital video clock jitter attenuation and frequency
translation. The device contains two internal frequency multiplication
stages that are cascaded in series. The first stage is a VCXO PLL
that is optimized to provide reference clock jitter attenuation, and to
support the complex PLL multiplication ratios needed for video rate
conversion.
The second stage is a FemtoClock™ frequency multiplier that
provides the low jitter, high frequency video output clock.
Preset multiplication ratios are selected from internal lookup tables
using device input selection pins. The multiplication ratios are
optimized to support common video rates used in professional video
system applications. The VCXO requires the use of an external,
inexpensive pullable crystal. Two crystal connections are provided
(pin selectable) so that both 60 and 59.94Hz base frame rates can
be supported. The VCXO requires external passive loop filter
components which are used to set the PLL loop bandwidth and
damping characteristics.
Features
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Jitter attenuation and frequency translation of video clock signals
Supports SMTPE 292M, ITU-R Rec. 601/656 and
MPEG-transport clocks
Support of High-Definition (HD) and Standard-Definition (SD) pixel
rates
Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates
in one device
Dual PLL mode for high-frequency clock generation (32.967MHz
to 162MHz)
VCXO-PLL mode for low-frequency clock generation (27MHz and
26.973MHz)
One LVCMOS/LVTTL PLL clock output
Two selectable LVCMOS/LVTTL input clocks
LVCMOS/LVTTL compatible control signals
RMS phase jitter @148.5MHz, using a 27MHz crystal
(12kHz – 20MHz): 1.01ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in a lead-free (RoHS 6) 32-VFQFN package
Use replacement part: 8T49N241-dddNLGI
Supported Input Frequencies
f
VCXO
= 27MHz
67.5kHz
56.25kHz
45.0kHz
37.5kHz
33.75kHz
31.4685kHz
31.25kHz
28.125kHz
27.0kHz
22.5kHz
18.75kHz
18kHz
15.7343kHz
15.625kHz
f
VCXO
= 26.973MHz
67.4326
56.1938
44.955
37.4625
33.7163
31.4371
31.2188
28.0969
26.973
22.4775
18.7313
17.982
15.7185
15.6094
Supported Output Frequencies
f
VCXO
= 27MHz
148.5
74.25
49.5
33
162
81
54
36
27
f
VCXO
= 26.973MHz
148.3516
74.1758
49.4505
32.967
161.8382
80.9191
53.9461
35.9640
26.973
810001-22 Rev A 8/14/15
1
©2015 Integrated Device Technology, Inc.
810001-22 DATA SHEET
Block Diagram
XTAL_OUT0
XTAL_IN0
XTAL_IN1
XTAL_OUT1
XTAL_SEL
Loop
Filter
ISET
LF0
LF1
0
Phase
Detector
1
CLK0
CLK1
CLK_SEL
V3:V0
4
0
1
VCXO
Charge
Pump
VCXO Feedback Divider
(M Value from Table)
VCXO
Divider
Table
VCXO Jitter Attenuation PLL
10
11
FemtoClock
Frequency Multiplier
0= x22
1= x24
01
10
11
Output
Divider
00 = 4
01 = 8
10 = 12
11 = 18
00
01
10
11
Q
OE
MR
MF
N1:N0
nBP1:nBP0
2
2
Master Reset
Pin Assignment
XTAL_OUT0
XTAL_OUT1
XTAL_IN0
XTAL_IN1
GND
XTAL_SEL
V
DDX
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
DD
nBP0
GND
CLK_SEL
CLK1
1
2
3
4
5
6
7
8
9
CLK0
V
DD
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
V1
V0
V
DD
MR
MF
V2
V3
N0
N1
nBP1
OE
GND
Q
V
DDO
V
DDA
810001-22
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
2
Rev A 8/14/15
810001-22 DATA SHEET
Table 1. Pin Descriptions
Number
1, 2
3
4, 11, 25
5, 22
6, 20, 29
7
8, 9
10, 14,
15, 16
12
13
17
18
19
21
23, 24
26
27,
28
30,
31
32
Name
LF1, LF0
ISET
V
DD
nBP0,
nBP1
GND
CLK_SEL
CLK1, CLK0
V0, V1,
V2, V3
MR
MF
V
DDA
V
DDO
Q
OE
N1, N0
XTAL_SEL
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
V
DDX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Description
Loop filter connection node pins.
Charge pump current setting pin.
Core supply pins.
PLL Bypass control pins. See block diagram.
Power supply ground.
Input clock select. When HIGH selects CLK1. When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the output to go low. When logic LOW, the internal dividers and the
output is enabled. LVCMOS/LVTTL interface levels.
FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
Output supply pin.
Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels.
Pullup
Pulldown
Pulldown
Output enable. When logic LOW, the clock output is in high-impedance. When
logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels.
FemtoClock output divide select pins. LVCMOS/LVTTL interface levels.
Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output.
Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output.
Power supply pin for VCXO charge pump.
Input
Input
Power
Power
Output
Input
Input
Input
Input
Input
Power
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= V
DDO
= 3.465V
Test Conditions
Minimum
Typical
4
8.5
51
51
22.5
Maximum
Units
pF
pF
k
k
Rev A 8/14/15
3
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
810001-22 DATA SHEET
Function Tables
Table 3A. VCXO PLL Feedback Divider and Input Frequency Function Table
Input
V3
0 (default)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
V2
0 (default)
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
V1
0 (default)
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V0
0 (default)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCXO PLL Configuration
Feedback-Divider M
400
480
600
720
800
858
864
960
1000
1200
1440
1500
1716
1728
1716
960
Input frequency for crystal frequency (f
VCXO
) in kHz
f
VCXO
= 27MHz
67.5
56.25
45.00
37.50
33.75
31.4685
31.25
28.125
27.00
22.50
18.75
18.00
15.7343
15.6250
15.7343
28.125
f
VCXO
= 26.973MHz
67.4326
56.1938
44.9550
37.4625
33.7163
31.4371
31.2188
28.0969
26.973
22.4775
18.7313
17.9820
15.7185
15.6094
15.7185
28.0969
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
4
Rev A 8/14/15
810001-22 DATA SHEET
Table 3B. Output Frequency Table (Dual PLL Mode)
FemtoClock Look-up Table
f
VCXO
MF
0
0
0
0
27MHz
1
1
1
1
0
0
0
0
26.973MHz
1
1
1
1
0
0
1
1
0
1
0
1
161.8382
80.9191
53.9461
35.9640
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
162.0000
81.0000
54.0000
36.0000
148.3515
74.1758
49.4505
32.9670
N1
0
0
1
1
N0
0
1
0
1
Output Frequency f
Q
(MHz)
148.5000
74.2500
49.5000
33.0000
NOTE: Use the VCXO-PLL mode to achieve output frequencies of 27MHz or 26.973MHz. See Table 3G.
Table 3C. CLK_SEL Function Table
Input
CLK_SEL
0 (default)
1
Operation
Selects CLK0 as PLL reference input.
Selects CLK1 as PLL reference input.
Table 3D. MR Master Reset Function Table
Input
MR
0 (default)
1
Operation
Normal operation, internal dividers and the output Q are enabled.
Internal dividers are reset. Q output is in logic low state (with OE = 1).
Table 3E. FemtoCLock PLL Feedback Divider Function Table
Input
MF
0 (default)
1
Operation
Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22.
Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24.
Rev A 8/14/15
5
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
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