DATASHEET
LOCO™ PLL CLOCK MULTIPLIER
Description
The ICS512 is the most cost effective way to generate
a high-quality, high frequency clock output and a
reference clock from a lower frequency crystal or clock
input. The name LOCO stands for Low Cost Oscillator,
as it is designed to replace crystal oscillators in most
electronic systems. Using Phase-Locked-Loop (PLL)
techniques, the device uses a standard fundamental
mode, inexpensive crystal to produce output clocks up
to 200 MHz. With a reference output, this chip plus an
inexpensive crystal can replace two oscillators
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
ICS512
Features
•
Packaged as 8-pin SOIC or die
•
Pb (lead ) free package
•
Upgrade of popular ICS502 with:
— changed multiplier table
— higher operating frequncies
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•
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•
•
•
•
•
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Zero ppm multiplication error
Easy to cascade with other 5xx series
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 200 MHz
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Mask option for nine selectable frequencies
Operating voltages of 3.0 to 5.5 V
Industrial temperature version available
Advanced, low power CMOS process
Block Diagram
VDD
S1, S0
X1/ICLK
Crystal or
Clock input
X2
Optional crystal
capacitors
2
PLL Clock
Synthesis
and Control
Circuitry
CLK
Crystal
Oscillator
REF
GND
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
1
ICS512
REV H 051310
ICS512
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
X1/ I CLK
VDD
GND
REF
1
2
3
4
8
7
6
5
X2
S1
S0
CLK
Clock Output Table
S1
0
0
0
M
M
M
1
1
1
S0
0
M
1
0
M
1
0
M
1
CLK
4X input
5.333X input
5X input
2.5X input
2X input
3.333X input
6X input
3X input
8X input
8 - p i n ( 1 5 0 mi l ) S OI C
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequencies Example (MHz)
Output
Input
Selection (S1, S0)
Output
Input
Selection (S1, S0)
20
10
M,M
66.66
20
M,1
24
12
M,M
72
12
1,0
30
10
1, M
75
25
1,M
32
16
M,M
80
10
1,1
33.33
16.66
M,M
83.33
25
M,1
37.5
15
M,0
90
15
1,0
40
10
0,0
100
20
0,1
48
12
0,0
120
15
1,1
50
20
M,0
125
25
0,1
60
10
1,0
133.3
25
0,M
64
16
0,0
150
25
1,0
Note that all of the above are achieved using a common, inexpensive 10 MHz to 25 MHz crystal. Consult
IDT on how to achieve other output frequncies.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
2
ICS512
REV H 051310
ICS512
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
NC
CLK
S0
S1
X2
Pin Type
Input
Power
Power
REF
Output
Tri-level Input
Tri-level Input
Output
Pin Description
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Buffered crystal oscillator output clock.
Clock output per table above.
Mulitplier select pin 0. Connect to GND or VDD or float.
Mulitplier select pin 1. Connect to GND or VDD or float.
Crystal connection. Leave unconnected for clock input.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
3
ICS512
REV H 051310
ICS512
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS512 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and GND. It must be connected close to
the ICS512 to minimize lead inductance. No external
power supply filtering is required for the ICS512.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
pin. The total on-chip capacitance is approximately 12
pF. A parallel resonant, fundamental mode crystal
should be used.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS512. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+3.0
Typ.
Max.
+70
+85
+5.0
Units
°
C
°
C
V
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
4
ICS512
REV H 051310
ICS512
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=3.3 V ±5%
, Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Output High Voltage, CMOS high
Output High Voltage
Output Low Voltage
IDD Operating Supply Current,
20 MHz crystal
Short Circuit Current
Input Capacitance, S1, S0
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
S0, S1
S0, S1
I
OH
= -8 mA
I
OH
= -12 mA
I
OL
= 12 mA
No load, 100 MHz
CLK output
Pins 6, 7
Min.
3
Typ.
Max.
5.5
Units
V
V
V
V
V
V
V
(VDD/2)+1 VDD/2
VDD/2
VDD-0.5
0.5
VDD-0.4
2.4
0.4
9
+70
4
(VDD/2)-1
V
mA
mA
pF
AC Electrical Characteristics
VDD=3.3 V ±5%,
Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5 V
Output Frequency, VDD = 3.0 to 3.6 V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
F
IN
F
IN
F
OUT
F
OUT
t
OR
t
OF
t
OD
t
ja
t
js
Conditions
Min.
5
2
Typ.
Max.
27
50
200
160
160
145
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
0 to +70°C
-40 to +85°C
0 to +70°C
-40 to +85°C
0.8 to 2.0 V
2.0 to 8.0V
at VDD/2
Deviation from
mean
14
14
14
14
1
1
45
49-51
+200
80
55
%
ps
ps
Note: The phase relationship between intput and output clocks can change at power up. For a fixed phase
relationship, see the ICS570 or the ICS527.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
5
ICS512
REV H 051310
微控制器 MCU
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