74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs
September 2001
Revised February 2002
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26
Ω
Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26
Ω
series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) V
CC
applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s
26
Ω
series resistors in outputs
s
t
PD
4.2 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
7.6 ns max for 1.65V to 1.95V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Order Number
74ALVCH162244T
Package
Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation
DS500632
www.fairchildsemi.com
74ALVCH162244
Connection Diagram
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
Inputs
OE
3
L
L
H
Inputs
OE
4
L
L
H
L
H
X
I
12
–I
15
L
H
Z
L
H
X
I
8
–I
11
L
H
Z
Outputs
O
12
–O
15
L
H
X
I
4
–I
7
L
H
Z
Outputs
O
8
–O
11
I
0
–I
3
L
H
X
Outputs
O
4
–O
7
Outputs
O
0
–O
3
L
H
Z
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
Functional Description
The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain
full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OE
n
) input. When OE
n
is LOW, the outputs
are in the 2-state mode. When OE
n
is HIGH, the standard outputs are in the high impedance mode but this does not inter-
fere with entering new data into the inputs.
Logic Diagram
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2
74ALVCH162244
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 2)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 3)
Power Supply
Operating
Input Voltage
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 2:
I
O
Absolute Maximum Rating must be observed.
Note 3:
Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −2
mA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −8
mA
I
OH
= −12
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
2 mA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
8 mA
I
OL
=
12 mA
I
I
I
I(HOLD)
Input Leakage Current
Bushold Input Minimum
Drive Hold Current
0
≤
V
I
≤
3.6V
V
IN
=
0.58V
V
IN
=
1.07V
V
IN
=
0.7V
V
IN
=
1.7V
V
IN
=
0.8V
V
IN
=
2.0V
0
<
V
O
≤
3.6V
I
OZ
I
CC
∆I
CC
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
1.65 - 3.6
1.65
2.3
2.3
3
2.7
3.0
1.65 - 3.6
1.65
2.3
2.3
3
2.7
3
3.6
1.65
1.65
2.3
2.3
3.0
3.0
3.6
3.6
3.6
3 - 3.6
25
−25
45
−45
75
−75
±500
±10
40
750
µA
µA
µA
µA
V
CC
- 0.2
1.2
1.9
1.7
2.4
2
2
0.2
0.45
0.4
0.55
0.55
0.6
0.8
±5.0
µA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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74ALVCH162244
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
, t
PHZ
SWITCH
Open
V
L
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
Ω
)
Symbol
V
mi
V
mo
V
X
V
Y
V
L
V
CC
3.3V
±
0.3V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.7V
1.5V
1.5V
V
OL
+
0.3V
V
OH
−
0.3V
6V
2.5V
±
0.2V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
1.8V
±
0.15V
V
CC
/2
V
CC
/2
V
OL
+
0.15V
V
OH
−
0.15V
V
CC
*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5
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