Low Skew, 1-to-4, Differential-to-2.5V, 3.3V
LVPECL Fanout Buffer
ICS853S004I
DATA SHEET
General Description
The ICS853S004I is a low skew, high performance 1-to-4, 2.5V/3.3V
Differential-to-LVPECL Fanout Buffer. Guaranteed output and
part-to-part skew characteristics make the ICS853S004I ideal for
those applications demanding well defined performance and
repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Four differential LVPECL outputs
Differential LVPECL clock input pair
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
Maximum output frequency: 2GHz
Output skew: 25ps (maximum)
Part-to-part skew: 100ps (maximum)
Propagation delay: 500ps (maximum)
Additive Phase Jitter, RMS: 0.10ps (maximum) @156.25MHz
(12kHz - 20MHz)
Clock enable signal synchronized to eliminate runt clock pulses
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
ICS853S004I
16-Lead VFQFN
Top View
ICS853S004AKI May 27, 2017
1
©2017 Integrated Device Technology, Inc.
ICS853S004I Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7
8
9
10
11
12, 14
13
15, 16
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
V
EE
nc
PCLK
nPCLK
V
BB
V
CC
nEN
Q0, nQ0
Output
Output
Output
Power
Unused
Input
Input
Output
Power
Input
Output
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
No connect.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage.
Power supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
When HIGH, Qx outputs are forced low, nQx outputs are forced high.
Single-ended LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
37
37
Maximum
Units
k
k
ICS853S004AKI May 27, 2017
2
©2017 Integrated Device Technology, Inc.
ICS853S004I Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
nEN
1
0
Q[0:3]
Disabled; Low
Enabled
Outputs
nQ[0:3]
Disabled; High
Enabled
After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in
Figure 1.
In the active mode, the state of the outputs are a function of the PCLK/nPCLK input as described in Table 3B.
V
DD
/2
nEN
nPCLK
PCLK
V
DD
/2
t
H
t
S
V
PP
t
PD
nQ[0:3]
Q[0:3]
Figure 1. nEN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ3
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section,
Wiring the Differential Input to Accept Single-ended Levels.
ICS853S004AKI May 27, 2017
3
©2017 Integrated Device Technology, Inc.
ICS853S004I Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink//Source, I
BB
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-0.5V to V
CC
+ 0.5V
50mA
100mA
± 0.5mA
-40C to +85C
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
68
Units
V
mA
ICS853S004AKI May 27, 2017
4
©2017 Integrated Device Technology, Inc.
ICS853S004I Data Sheet
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 4B. DC Characteristics,
V
CC
= 3.3V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
CMR
V
PP
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
nEN
Input Low Voltage
25°C
Max
2.50
1.68
2.36
1.765
2.00
3.3
Min
2.165
1.40
2.075
1.43
1.72
1.2
150
800
Typ
2.295
1.52
Max
2.495
1.615
2.36
1.765
2.00
3.3
1200
150
-10
-150
-10
-150
Min
2.160
1.39
2.075
1.43
1.72
1.2
150
85°C
Typ
2.295
1.535
Max
2.485
1.63
2.36
1.765
2.00
3.3
800
1200
150
Units
V
V
V
V
V
V
mV
µA
µA
µA
Min
2.175
1.405
2.075
1.43
1.72
1.2
150
Typ
2.275
1.545
nEN
Output Voltage Reference;
NOTE 2
Input High Voltage Common
Mode Range; NOTE 3
Peak-to-Peak Input Voltage;
NOTE 4
Input
High Current
Input
Low Current
nEN, PCLK,
nPCLK
nEN, PCLK
nPCLK
800
1200
150
-10
-150
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.165V to -0.5V.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
NOTE 2: Single-ended input operation is limited. V
CC
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
for the differential inputs.
NOTE 4: The V
CMR
and V
PP
levels should be such that the input low voltage never goes below V
EE
.
Table 4C. LVPECL DC Characteristics,
V
CC
= 2.5V; V
EE
= 0V, T
A
= -40°C to 85°C
-40°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
CMR
V
PP
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
Input Low Voltage
25°C
Max
1.70
0.88
1.56
0.965
2.5
Min
1.425
0.625
1.275
0.63
1.2
150
800
Typ
1.495
0.72
Max
1.69
0.86
1.56
0.965
2.5
1200
150
-10
-150
-10
-150
Min
1.40
0.64
1.275
0.63
1.2
150
85°C
Typ
1.495
0.735
Max
1.685
0.85
1.56
0.965
2.5
800
1200
150
Units
V
V
V
V
V
mV
µA
µA
µA
Min
1.375
0.605
1.275
0.63
1.2
150
Typ
1.475
0.745
nEN
nEN
Input High Voltage Common
Mode Range; NOTE 2, 3
Peak-to-Peak Input Voltage;
NOTE 4
Input
High Current
Input
Low Current
nEN, PCLK,
nPCLK
nEN, PCLK
nPCLK
800
1200
150
-10
-150
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125V to -0.125V.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
NOTE 2: Common mode voltage is defined as V
IH
for the differential inputs.
NOTE 3: The V
CMR
and V
PP
levels should be such that the input low voltage never goes below V
EE
.
ICS853S004AKI May 27, 2017
5
©2017 Integrated Device Technology, Inc.
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
