74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Rev. 1 — 30 July 2012
Product data sheet
1. General description
The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches
designed for general-purpose storage applications in digital systems. They are
multifunctional devices capable of storing single-line data in eight addressable latches and
providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7).
They also incorporate an active LOW common reset (MR) for resetting all latches as well
as an active LOW enable input (LE).
The 74HC259-Q100; 74HCT259-Q100 has four modes of operation:
•
Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch follows the data input with all non-addressed
latches remaining in their previous states.
•
Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs.
•
Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state.
•
Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D).
When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing
more than one address bit could impose a transient wrong address. Therefore, this should
only be done while in the Memory mode.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Combined demultiplexer and 8-bit latch
Serial-to-parallel capability
Output from each storage bit available
Random (addressable) data entry
Easily expandable
Common reset input
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Useful as a 3-to-8 active HIGH decoder
Input levels:
For 74HC259-Q100: CMOS level
For 74HCT259-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HC259D-Q100
74HCT259D-Q100
74HC259PW-Q100
74HCT259PW-Q100
74HC259BQ-Q100
74HCT259BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very SOT763-1
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
13
15
14
Z9
G8
G10
9,10D
0
1
C10
8R
DX
14
LE
Q0
13
D
Q1
Q2
Q3
1
2
3
A0
A1
A2
MR
15
mna573
4
1
4
5
6
7
9
10
11
12
2
3
0
G
2
0
7
1
5
6
2
7
3
9
4
10
5
11
6
12
7
mna572
Q4
Q5
Q6
Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 July 2012
2 of 20
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Q0
1
2
3
A0
A1
A2
1-of-8
DECODER
8 LATCHES
14
15
13
LE
MR
D
Q1
Q2
Q3
Q4
4
5
6
7
9
Q5 10
Q6 11
Q7 12
mna571
Fig 3.
Functional diagram
5. Pinning information
5.1 Pinning
74HC259-Q100
74HCT259-Q100
terminal 1
index area
A1
16 V
CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9
aaa-003386
74HC259-Q100
74HCT259-Q100
A0
A1
A2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
Q4
9
GND
(1)
16 V
CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
A2
Q0
Q1
Q2
Q3
1
A0
Q4
aaa-003387
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 4.
Pin configuration (SO16 and TSSOP16)
Fig 5.
Pin configuration (DHVQFN16)
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 July 2012
3 of 20
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
5.2 Pin description
Table 2.
Symbol
A0, A1, A2
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
D
LE
MR
V
CC
Pin description
Pin
1, 2, 3
8
13
14
15
16
Description
address input
ground (0 V)
data input
latch enable input (active LOW)
conditional reset input (active LOW)
supply voltage
4, 5, 6, 7, 9, 10, 11, 12 latch output
6. Functional description
Table 3.
Function table
[1]
Input
MR
Reset (clear)
L
Demultiplexer
L
(active HIGH 8-channel) L
decoder (when D = H)
L
L
L
L
L
L
Memory (no action)
Addressable latch
H
H
H
H
H
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Operating mode
Output
LE
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
D
X
d
d
d
d
d
d
d
d
X
d
d
d
d
d
d
d
d
A0
X
L
H
L
H
L
H
L
H
X
L
H
L
H
L
H
L
H
A1
X
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
A2
X
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
Q0
L
L
L
L
L
L
L
L
q
0
q
0
q
0
q
0
q
0
q
0
q
0
q
0
Q1
L
Q2
L
L
Q3
L
L
L
Q4
L
L
L
L
Q5
L
L
L
L
L
Q6
L
L
L
L
L
L
Q7
L
L
L
L
L
L
L
Q=d
q
7
q
7
q
7
q
7
q
7
q
7
q
7
Q=d
Q=d L
L
L
L
L
L
L
q
1
Q=d L
L
L
L
L
L
q
2
q
2
Q=d L
L
L
L
L
q
3
q
3
q
3
Q=d L
L
L
L
q
4
q
4
q
4
q
4
Q=d L
L
L
q
5
q
5
q
5
q
5
q
5
Q=d L
L
q
6
q
6
q
6
q
6
q
6
q
6
Q=d L
Q = d q
1
q
1
q
1
q
1
q
1
q
1
q
1
Q = d q
2
q
2
q
2
q
2
q
2
q
2
Q = d q
3
q
3
q
3
q
3
q
3
Q = d q
4
q
4
q
4
q
4
Q = d q
5
q
5
q
5
Q = d q
6
q
6
Q = d q
7
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 July 2012
4 of 20
Nexperia
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Table 4.
LE
L
H
L
H
[1]
Operating mode select table
[1]
MR
H
H
L
L
Mode
Addressable latch mode
Memory mode
Demultiplexer mode
Reset mode
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
70
65
[2]
Max
+7.0
20
20
25
+70
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT259_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 1 — 30 July 2012
5 of 20
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
