IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
BUFFER/DRIVER WITH
3-STATE OUTPUTS
FEATURES:
DESCRIPTION:
IDT74ALVC16244A
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
μ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
This 16-bit buffer/driver is built using advanced dual metal CMOS
technology. The ALVC16244A is designed specifically to improve the
performance and density of 3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters. The device can be used as
four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true
outputs and symmetrical active-low output-enable (OE) inputs.
The ALVC16244A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
3
OE
25
1
A
1
47
2
1
Y
1
3
A
1
36
13
3
Y
1
1
A
2
46
3
1
Y
2
3
A
2
35
14
3
Y
2
1
A
3
44
5
1
Y
3
3
A
3
33
16
3
Y
3
1
A
4
43
6
1
Y
4
3
A
4
32
17
3
Y
4
2
OE
48
4
OE
24
2
A
1
41
8
2
Y
1
4
A
1
30
19
4
Y
1
2
A
2
40
9
2
Y
2
4
A
2
29
20
4
Y
2
2
A
3
38
11
2
Y
3
4
A
3
27
22
4
Y
3
2
A
4
37
12
2
Y
4
4
A
4
26
23
4
Y
4
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
©2016 Integrated Device Technology, Inc.
JUNE 2016
DSC-4698/7
IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
Y
1
1
Y
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
Unit
V
V
°C
mA
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSSOP
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
OE
1
A
1
1
A
2
V
TERM
(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
1
Y
3
1
Y
4
GND
1
A
3
1
A
4
V
CC
2
Y
1
2
Y
2
V
CC
2
A
1
2
A
2
GND
2
Y
3
2
Y
4
3
Y
1
3
Y
2
GND
2
A
3
2
A
4
3
A
1
3
A
2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
GND
3
Y
3
3
Y
4
GND
3
A
3
3
A
4
NOTE:
1. As applicable to the device type.
V
CC
4
Y
1
4
Y
2
V
CC
4
A
1
4
A
2
PIN DESCRIPTION
Pin Names
xOE
xAx
xYx
Data Inputs
3-State Outputs
Description
3-State Output Enable Inputs (Active LOW)
GND
4
Y
3
4
Y
4
4
OE
GND
4
A
3
4
A
4
3
OE
FUNCTION TABLE
(1)
Inputs
xOE
L
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
Outputs
xAx
H
L
X
xYx
H
L
Z
2
IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
ΔI
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
–0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
±10
±10
–1.2
—
40
V
mV
μA
μA
μA
μA
V
Unit
V
Quiescent Power Supply Current
Variation
—
—
750
μA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
16
4
V
CC
= 3.3V ± 0.3V
Typical
19
5
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK(
o
)
Parameter
Propagation Delay
xA to xBx
Output Enable Time
OE
to xBx
Output Disable Time
OE
to xBx
Output Skew
(2)
—
—
—
—
—
500
ps
1
5.8
—
5.2
1
5
ns
1
6.3
—
6
1
5
ns
Min.
1
Max.
4.4
—
V
CC
= 2.7V
Min.
Max.
4
V
CC
= 3.3V ± 0.3V
Min.
1
Max.
3.6
Unit
ns
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALVC Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
500Ω
Pulse
Generator
(1, 2)
SAME PHASE
INPUT TRANSITION
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
6
2.7
1.5
300
300
50
t
PHL
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
DISABLE
V
IN
D.U.T.
R
T
V
OUT
t
PLZ
V
IH
V
T
0V
V
LOAD/2
V
OL
+ V
LZ
V
OL
V
OH
V
OH -
V
HZ
0V
ALVC Link
500Ω
C
L
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2ns; t
R
≤
2ns.
V
LOAD/2
OUTPUT
SWITCH
V
T
NORMALLY
CLOSED
LOW
t
PHZ
t
PZH
OUTPUT
SWITCH
NORMALLY
V
T
OPEN
HIGH
0V
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH2
t
PHL2
ALVC Link
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALVC Link
Set-up, Hold, and Release Times
INPUT
t
PLH1
t
PHL1
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
ALVC Link
OUTPUT 2
Pulse Width
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
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