HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
IDT7025S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
◆
◆
◆
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◆
◆
◆
◆
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◆
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Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
A
12L
A
0L
(1,2)
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
A
12R
A
0R
(1,2)
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(2)
2683 drw 01
M/S
MARCH 2018
1
DSC 2683/12
©2018 Integrated Device Technology, Inc.
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7025 is a high-speed 8K x 16 Dual-Port Static RAM. The
IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 32-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by Chip Enable (CE) permits the on-chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-pin
Flatpack, PLCC, and a 100-pin TQFP. Military grade product is manu-
factured in compliance with the latest revision of MIL-PRF-38535 QML,
making it ideally suited to military temperature applications demanding the
highest level of performance and reliability.
Pin Configurations
(1,2,3)
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
V
CC
SEM
L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
R/W
L
INDEX
CE
L
UB
L
LB
L
A
12L
A
11L
A
10L
A
9L
A
8L
11/06/01
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
72
14
71
15
70
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IDT7025J or F
J84-1
(4)
F84-2
(4)
84-Pin PLCC/Flatpack
Top View
(5)
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
2683 drw 02
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
V
CC
R/W
L
SEM
L
CE
L
UB
L
LB
L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
2
74
3
73
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
31
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O
14R
GND
I/O
15R
GND
SEM
R
CE
R
UB
R
LB
R
A
12R
A
11R
A
10R
A
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
OE
R
R/W
R
I/O
9R
A
8R
A
7R
Index
11/06/01
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
.
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
IDT7025PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
2683 drw 03
6.42
2
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
11/06/01
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
11L
44
A
10L
43
A
7L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
A
12L
A
9L
A
8L
41
A
5L
39
09
I/O
11L
69
I/O
9L
68
GND
V
CC
R/W
L
A
6L
38
A
4L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
3L
35
A
2L
34
07
I/O
15L
75
I/O
14L
70
V
CC
74
BUSY
L
IDT7025G
G84-3
(4)
84-Pin PGA
Top View
(5)
32
A
0L
31
INT
L
36
06
I/O
0R
76
GND
77
GND
78
GND
28
M/S
29
A
1L
30
05
I/O
1R
79
I/O
2R
80
V
CC
A
0R
INT
R
26
BUSY
R
27
04
I/O
3R
81
I/O
4R
83
7
11
12
A
2R
23
A
1R
25
03
I/O
5R
82
1
I/O
7R
2
5
GND
8
GND
10
SEM
R
14
17
20
A
5R
22
A
3R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/W
R
15
UB
R
13
A
11R
16
A
8R
18
A
6R
19
A
4R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
A
12R
H
A
10R
J
A
9R
K
A
7R
L
2683 drw 04
.
Index
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
12L
I/O
0L
- I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
12R
I/O
0R
- I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2683 tbl 01
Names
6.42
4
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
X
L
L
L
L
L
L
X
NOTE:
Outputs
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Deselected
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
2683 tbl 02
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
Mode
1. A
0L
— A
12L
≠
A
0R
— A
12R.
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
X
H
X
L
L
R/W
H
H
↑
↑
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Outputs
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Mode
Read Semaphore Flag Data Out
Read Semaphore Flag Data Out
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
2683 tbl 03
NOTES:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0
- I/O
15.
These eight semaphores are addressed by A
0
- A
2
.
6.42
5
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