MDT2051
1. General Description
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This EPROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed
and
smaller
size
with
the
low
power
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A/D converter module:
-Four analog inputs multiplexed into one A/D
converter
-8-bit resolution
4 types of oscillator can be selected by
programming option:
RC－Low cost RC oscillator
LFXT－Low frequency crystal oscillator
consump-tion and high noise immunity. On chip
memory incl-udes 1K words of ROM, and 68 b
ytes of
static RAM.
2. Features
The followings are some of the features on the
hardware and software :
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Fully CMOS static design
8-bit data bus
On chip EPROM size : 1.0 K words
Internal RAM size : 84 bytes
(68 general purpose registers, 16 special
registers)
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37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.5 V ~ 5.5 V (PRD Disable)
4.5 V ~ 5.5 V (PRD Enable)
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Operating frequency : DC ~ 20 MHz
The most fast execution time is 200 ns under
20 MHz in all single cycle instructions except
the branch instruction
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Addressing modes include direct, indirect and
relative addressing modes
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Power-on Reset
Power edge-detector Reset
Power range-detector Reset
Sleep Mode for power saving
Four interrupt sources:
-External INT pin
-TMR0 timer
-A/D conversion completion
-PortB<7:4> interrupt on change
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XTAL－Standard crystal oscillator
HFXT－High frequency crystal oscillator
8-bit real time clock/counter(RTCC) with 8-bit
programmable prescaler
On-chip RC oscillator based Watchdog
Timer(WDT)
13 I/O pins with their own independent
direction control
3. Applications
The application areas of this MDT2051 range from
appliance motor control and high speed automotive
to low power remote transmitters/receivers, pointing
devices, and telecommunications processors, such
as Remote controller, small instruments, chargers,
toy, automobile and PC peripheral … etc.
4. Pin Assignment
PA2/AIC2
PA3/AIC3
PA4/RTCC
/MCLR
V
ss
PB0/INT
PB1
PB2
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
10
PA1/AIC1
PA0/AIC0
OSC1
OSC2
V
dd
PB7
PB6
PB5
PB4
PB3 9
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 1
2004/1
Ver. 1.8
MDT2051
5. Pin Function Description
Pin Name
PA0~PA3
PB0~PB7
I/O
I/O
I/O
Function Description
Port A, TTL input level / Analog input channel
Port B, TTL input level / PB0:External interrupt input ,
PB4~PB7:Interrupt on pin change
RTCC/PA4
I/O
Real Time Clock/Counter, Schmitt Trigger input levels
Open drain output
/MCLR
OSC1
OSC2
V
dd
V
ss
I
I
O
Master Clear, Schmitt Trigger input levels
Oscillator Input
Oscillator Output
Power supply
Ground
6. Memory Map
(A) Register Map
Address
BANK0
00
01
02
03
04
05
06
08
09
0A
0B
0C~4F
BANK1
01
05
TMR
CPIO A
Indirect Addressing Register
RTCC
PCL
STATUS
MSR
Port A
Port B
ADS0
ADRES
PCH
INTS
General purpose register
Description
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 2
2004/1
Ver. 1.8
MDT2051
Address
06
07
08
CPIO B
PSTA
ADS1
Description
(1)IAR ( Indirect Address Register) : R00
(2)RTCC (Real Time Counter/Counter Register) : R01
(3) PC (Program Counter) : R02,R0A
Write PC --- from PCH
LJUMP, LCALL --- from instruction word
RTIW, RET,RTFI --- from STACK
A9
A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTIW, RET, RTFI --- from STACK
(4) STATUS (Status register) : R03
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
PF
TF
RBS0
Carry bit
Half Carry bit
Zero bit
Function
Power down Flag bit
WDT Timer overflow Flag bit
Register Bank Select bit :
0 : 00H --- 7FH
1 : 80H --- FFH
7~6
——
General purpose bit
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 3
2004/1
Ver. 1.8
MDT2051
(5) MSR (Memory Bank Select Register) : R4
Memory Bank Select Register :
0 : 00~7F
1 : 80~FF
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A : R05
PA4~PA0, I/O Register
(7) PORT B : R06
PB7~PB0, I/O Register
(8) ADS0 ( A/D Status Register ) : R08
Bit
0
Symbol
ADRUN
Function
0 : A/D converter module is shut off and consumes no operating current
1 : A/D converter module is operating
1
ADIF
A/D conversion complete interrupt flag bit
Set when conversion is completed. Reset in software.
2
GO/DONEB
GO/DONEB must be set to begin a conversion . It is automatically reset
in hardware when the conversion is complete
4,3
5
7,6
CHS1-0
Reserved
ASCS1-0
00 : AIC0 01 : AIC1 10 : AIC2
11 : AIC3
Can be used as a general purpose r/w bit
00 : fosc/2 01: fosc/8 10 : fosc/32 11 : f RC (*Note)
*Note: determined by OSC mode, HF: fosc/32 XT: fosc/8 RC: fosc/2 LF: fosc/2
(9) ADRES ( A/D result register ) : R09
(10)PCH (High byte of PC) : R0A
Bit
1~0
7~2
Function
High byte of PC
Unimplemented, reads as‘0’
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 4
2004/1
Ver. 1.8
MDT2051
(11) INTS ( Interrupt Status Register ) : R0B
Bit
0
1
2
3
Symbol
RBIF
INTF
TIF
RBIE
Function
PORT B change interrupt flag. Set when PB <7:4> inputs change
Set when INT interrupt occurs. INT interrupt flag.
Set when TMR overflows.
0 : disable PB change interrupt
1 : enable PB change interrupt
4
INTS
0 : disable INT interrupt
1 : enable INT interrupt
5
TIS
0 : disable TMR interrupt
1 : enable TMR interrupt
6
ADIS
0 : disable A/D interrupt
1 : enable A/D interrupt
7
GIS
0 : disable global interrupt
1 : enable global interrupt
(12) TMR (Time Mode Register) : R81
Bit
Symbol
Prescaler Value
0 0 0
0 0 1
0 1 0
0 1 1
2—0
PS2—0
1 0 0
1 0 1
1 1 0
Function
RTCC rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
WDT rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
1 1 1
1 : 256
1 : 128
Prescaler assignment bit :
0
—
RTCC
1
—
Watchdog Timer
RTCC signal Edge :
0
—
Increment on low-to-high transition on RTCC pin
1
—
Increment on high-to-low transition on RTCC pin
RTCC signal set :
0
—
Internal instruction cycle clock
1
—
Transition on RTCC pin
Interrupt edge select
0
—
Interrupt on falling edge on PB0
1
—
Interrupt on rising edge on PB0
PORTB pull-hi
0
—
PORTB pull-hi are enable
1
—
PORTB pull-hi are disable
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 5
2004/1
Ver. 1.8
FPGA/CPLD
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