Integrated
Circuit
Systems, Inc.
ICS87952I
L
OW
S
KEW
, 1-
TO
-11
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
EATURES
•
Fully integrated PLL
•
11 LVCMOS / LVTTL outputs, 7Ω typical output impedance
•
LVCMOS / LVTTL REF_CLK input
•
Output frequency range up to 180MHz at V
DD
= 3.3V ± 5%
•
VCO range: 240MHz to 480MHz
•
External feedback for “zero delay” clock regeneration
•
Cycle-to-cycle jitter: 100ps (typical)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Compatible with MPC952
G
ENERAL
D
ESCRIPTION
The ICS87952I is a low voltage, low skew LVCMOS/
LVTTL Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. With output frequencies up to
180MHz, the ICS87952I is targeted for high
performance clock applications. Along with a fully integrated PLL,
the ICS87952I contains frequency configurable outputs and an
external feedback input for regenerating clocks with “zero delay”.
,&6
For test and system debug purposes, the nPLL_EN input al-
lows the PLL to be bypassed. When HIGH, the MR/nOE input
resets the internal dividers and forces the outputs to the high
impedance state.
The low impedance LVCMOS/LVTTL outputs of the ICS87952I
are designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the ability
of each output to drive two series terminated transmission lines.
B
LOCK
D
IAGRAM
nPLL_EN
P
IN
A
SSIGNMENT
GNDO
GNDO
V
DDO
V
DDO
QB1
QB0
QA4
QA3
REF_CLK
PHASE
DETECTOR
VCO
240-480MHz
1
0
÷2
0
÷4/÷6
1
24 23 22 21 20 19 18 17
QA0
QA1
QA2
V
DDO
QB2
QB3
GNDO
GNDO
QC0
QC1
÷4/÷2
25
26
27
28
29
30
31
32
1
VCO_SEL
16
15
14
V
DDO
QA2
QA1
GNDO
QA0
V
DD
V
DDA
nPLL_EN
FB_IN
LFP
QA3
QA4
ICS87952I
13
12
11
10
9
VCO_SEL
F_SELA
QB0
QB1
V
DDO
2
F_SELC
3
F_SELB
4
F_SELA
5
MR/nOE
6
REF_CLK
7
GNDI
8
FB_IN
REV. A APRIL 30, 2003
F_SELB
QB2
QB3
÷2/÷4
QC0
QC1
F_SELC
MR/nOE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
87952AYI
www.icst.com/products/hiperclocks.html
1
Integrated
Circuit
Systems, Inc.
ICS87952I
L
OW
S
KEW
, 1-
TO
-11
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
Type
Input
Input
Input
Input
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
Name
VCO_SEL
F_SELC
F_SELB
F_SELA
Pulldown VCO select input. LVCMOS / LVTTL interface levels.
Determines output divider values for Bank C as described in Table 3A.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank B as described in Table 3A.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 3A.
Pulldown
LVCMOS / LVTTL interface levels.
Active High Master Reset. Active LOW output enable. When logic
LOW, the internal dividers and the outputs drivers are enabled.
Pulldown
When logic HIGH, the internal dividers are reset and the outputs
are tri-stated (HiZ). LVCMOS / LVTTL interface levels.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Internal power supply ground.
Feedback input to phase detector for generating clocks with
Pulldown
"zero delay". LVCMOS / LVTTL interface levels.
PLL select input. Selects between REF_CLK and the PLL.
Pulldown When HIGH, selects REF_CLK. When LOW, selects PLL.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pin.
Bank A clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output power supply ground.
Output supply pins.
Bank B clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
5
6
7
8
9
10
11
12, 14,
15, 18, 19
13, 17,
24, 28, 29
16, 20,
21, 25, 32
22, 23,
26, 27
30, 31
MR/nOE
REF_CLK
GNDI
FB_IN
nPLL_EN
V
DDA
V
DD
QA0, QA1,
QA2, QA3, QA4
GNDO
V
DDO
QB0, QB1,
QB2, QB3
QC0, QC1
Input
Input
Power
Input
Input
Power
Power
Output
Power
Power
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
V
DD
, V
DDA
, V
DDO
= 3.465V
25
7
Maximum
Units
pF
KΩ
pF
Ω
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
F_SELA
0
1
87952AYI
T
ABLE
3B. C
ONTROL
S
ELECT
F
UNCTION
T
ABLE
Input
F_SELC
0
1
Output
QC0:QC1
÷2
÷4
Control Input
VCO_SEL
MR/nOE
nPLL_EN
Logic 0
fVCO
Output Enable
Enable PLL
Logic 1
fVCO/2
HiZ
Disable PLL
REV. A APRIL 30, 2003
Output
QA0:QA4
÷4
÷6
Input
F_SELB
0
1
Output
QB0:QB3
÷4
÷2
www.icst.com/products/hiperclocks.html
2
Integrated
Circuit
Systems, Inc.
ICS87952I
L
OW
S
KEW
, 1-
TO
-11
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
15
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
160
20
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
REF_CLK,
Input
MR/nOE, FB_IN, VCO_SEL,
High Current
F_SELA:F_SELC, nPLL_EN
REF_CLK,
Input
MR/nOE, FB_IN, VCO_SEL,
Low Current
F_SELA:F_SELC, nPLL_EN
Output High Voltage
Output Low Voltage
Test Conditions
Minimum Typical
2
-0.3
V
DD
= V
IN
= 3.465V
Maximum
V
DD
+ 0.3
0.8
120
Units
V
V
µA
I
IL
V
OH
V
OL
V
DD
= 3.465V, V
IN
= 0V
I
OH
= -20mA
I
OL
= 20mA
-120
2.4
0.5
µA
V
V
T
ABLE
5. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Input Reference Frequency
NOTE: Input reference frequency is limited by
f
REF
the divider selection and the VCO lock range.
Test Conditions
Minimum
Typical
Maximum
100
Units
MHz
87952AYI
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3
REV. A APRIL 30, 2003
Integrated
Circuit
Systems, Inc.
ICS87952I
L
OW
S
KEW
, 1-
TO
-11
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
Test Conditions
QC, QB (
÷
2)
QA, QB, QC (
÷
4)
QA (
÷
6)
REF_CLK = 50MHz
Same Frequency
Same Frequency
Different Frequency
100
10
0.8V to 2.0V
0.10
t
Period
/2 - 750
1.5
2
t
Period
/2 - 500
1.0
t
Period
/2 + 750
8
10
Minimum
180
120
80
-200
240
0
200
480
350
450
550
Typical
Maximum
Units
MHz
MHz
MHz
ps
MHz
ps
ps
ps
ps
mS
ns
ps
ns
ns
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
f
VCO
Parameter
Maximum
Output Frequency
(PLL Mode)
REF_CLK to FB_IN Delay; NOTE 1
PLL VCO Lock Range
Excluding QA0
Output Skew;
NOTE 2, 3
All Outputs
All Outputs
t
sk(o)
t
jit(cc)
t
L
t
R
/ t
F
t
PW
t
PLZ
, t
PHZ
t
PZL
Cycle-to-Cycle Jitter; NOTE 3
PLL Lock Time
Output Rise/Fall Time
Output Pulse Width
Output Disable Time
Output Enable Time
All parameters measured at f
MAX
unless noted otherwise.
All outputs loaded at 50
Ω
to V
DDO
/2.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
87952AYI
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4
REV. A APRIL 30, 2003
Integrated
Circuit
Systems, Inc.
ICS87952I
L
OW
S
KEW
, 1-
TO
-11
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
, V
DDA
, V
DDO
= 1.65V±5%
SCOPE
Qx
V
DDO
2
LVCMOS
Qx
V
DDO
Qy
2
tsk(o)
GND = -1.65V±5%
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
V
DDO
V
DDO
V
DDO
2V
0.8V
t
R
2V
0.8V
t
F
n
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
C
YCLE
-
TO
-C
YCLE
J
ITTER
REF_CLK
V
DD
2
FB_IN
t
PD
V
DDO
2
REF_CLK
TO
FB_IN D
ELAY
87952AYI
➤
➤
QAx,
QBx,
QCx
2
2
2
t
cycle
t
cycle n+1
➤
Clock
Outputs
O
UTPUT
R
ISE
/F
ALL
T
IME
V
DDO
V
DDO
2
t
PW
t
PERIOD
V
DDO
2
QAx,
QBx,
QCx
2
t
PW
& t
P
ERIOD
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5
REV. A APRIL 30, 2003
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