Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS C
LOCK
G
ENERATOR
F
EATURES
• 10 single ended LVCMOS outputs, 7Ω typical output
impedance
• Selectable CLK0 and CLK1 LVCMOS clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• Maximum input/output frequency: 150MHz
• Output skew: 350ps (maximum)
• 3.3V input, 3.3V outputs
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC946
ICS87946I
G
ENERAL
D
ESCRIPTION
The ICS87946I is a low skew, ÷1, ÷2 LVCMOS
Clock Generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87946I has two select-
able single ended clock inputs. The single ended
clock inputs accept LVCMOS or LVTTL input levels. The low
impedance LVCMOS outputs are designed to drive 50Ω series
or parallel terminated transmission lines. The effective fanout
can be increased from 10 to 20 by utilizing the ability of the
outputs to drive two series terminated lines.
,&6
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946I is characterized at 3.3V core/3.3V output. Guar-
anteed output and part-to-part skew characteristics make the
ICS87946I ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_SEL
CLK0
CLK1
DIV_SELA
0
QB0:QB2
1
DIV_SELB
0
QC0:QC3
1
DIV_SELC
MR/nOE
0
1
÷1
÷2
0
QA0:QA2
1
P
IN
A
SSIGNMENT
MR/nOE
GND
GND
V
DDA
V
DDA
QA0
QA1
QA2
32 31 30 29 28 27 26 25
CLK_SEL
V
DD
CLK0
CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DDC
QC0
GND
QC1
V
DDC
QC2
GND
QC3
24
23
22
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
ICS87946I
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
87946AYI
www.icst.com/products/hiperclocks.html
1
REV. B OCTOBER 27, 2008
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS C
LOCK
G
ENERATOR
Type
Input
Power
Input
Input
Input
Input
Power
Power
Output
Description
Clock select input. When HIGH, selects CLK1. When LOW,
Pulldown
selects CLK0. LVCMOS / LVTTL interface levels.
Positive supply pins.
Pullup
ICS87946I
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6
7
8, 11, 15,
20, 24, 27,
31
9, 13, 17
10, 12,
14, 16
18, 22
Name
CLK_SEL
V
DD
CLK0, CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
V
DDC
QC0, QC1,
QC2, QC3
V
DDB
LVCMOS / LVTTL clock inputs.
Controls frequency division for Bank A outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank C outputs.
Pulldown
LVCMOS / LVTTL interface levels.
Power supply ground.
Positive supply pins for Bank C outputs.
Bank C outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Power
Positive supply pins for Bank B outputs.
Bank B outputs. LVCMOS / LVTTL interface levels.
19, 21, 23 QB2, QB1, QB0 Output
7Ω typical output impedance.
25, 29
V
DDA
Power
Positive supply pins for Bank A outputs.
26, 28,
Bank A outputs. LVCMOS / LVTTL interface levels.
QA2, QA1, QA0 Output
30
7Ω typical output impedance.
Master reset and output enable When LOW, output drivers are
32
MR/nOE
Input
Pulldown enabled. When HIGH, output drivers are in HiZ and dividers are
reset. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance (per output);
NOTE 1
Output Impedance
51
51
V
DD
, V
DDx
= 3.6V
25
7
Test Conditions
Minimum Typical
Maximum
4
Units
pF
KΩ
KΩ
pF
Ω
NOTE 1: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
.
T
ABLE
3. F
UNCTION
T
ABLE
MR/nOE
1
0
0
0
0
0
0
87946AYI
DIV_SELA
X
0
1
X
X
X
X
Inputs
DIV_SELB
X
X
X
0
1
X
X
DIV_SELC
X
X
X
X
X
0
1
QA0:QA2
Hi Z
fIN/1
fIN/2
Active
Active
Active
Active
Outputs
QB0:QB2
Hi Z
Active
Active
fIN/1
fIN/2
Active
Active
QC0:QC3
Hi Z
Active
Active
Active
Active
fIN/1
fIN/2
REV. B OCTOBER 27, 2008
www.icst.com/products/hiperclocks.html
2
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS C
LOCK
G
ENERATOR
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDx
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS87946I
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
DD
Outputs, V
DDx
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
X
Symbol
V
DD
V
DDx
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.6
3.6
85
Units
V
V
mA
NOTE 1: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
.
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
X
Symbol
Parameter
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
DIV_SELA, DIV_SELB,
DIV_SELC, CLK_SEL,
MR/nOE
CLK0, CLK1
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
120
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
IH
Input High Current
V
DD
= V
IN
= 3.6V
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
I
OH
= -20mA
I
OL
= 20mA
-5
-120
2.5
I
IL
V
OH
V
OL
Input Low Current
Output High Voltage
Output Low Voltage
0.4
V
87946AYI
www.icst.com/products/hiperclocks.html
3
REV. B OCTOBER 27, 2008
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS C
LOCK
G
ENERATOR
X
ICS87946I
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±0.3V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tp
HL
Parameter
Input Frequency
Propagation Delay,
Low to High; NOTE 1
Propagation Delay,
High to Low; NOTE 1
Output Skew; NOTE 2, 6
Multiple Frequency Skew;
NOTE 3, 6
Par t-to-Par t Skew; NOTE 4, 6
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
Output Enable Time; NOTE 5
0.8V to 2.0V
0.8V to 2.0V
0.1
0.1
f
MAX
< 100MHz
f
MAX
> 100MHz
Test Conditions
Minimum
150
2
2
12.0
11.5
350
350
450
4.5
1.0
1.0
11
Typical
Maximum
Units
MHz
ns
ns
ps
ps
ps
ns
ns
ns
ns
ns
t
sk(o)
t
sk(w)
t
sk(pp)
t
R
t
F
t
EN
Output Disable Time; NOTE 5
11
t
DIS
NOTE 1: Measured from the V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 2: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at V
DDx
/2.
NOTE 3: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDx
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE: V
DDx
denotes V
DDA
, V
DDB
, V
DDC
.
87946AYI
www.icst.com/products/hiperclocks.html
4
REV. B OCTOBER 27, 2008
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS C
LOCK
G
ENERATOR
ICS87946I
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
, V
DDx
= 1.65V±0.15V
SCOPE
Qx
V
DD
x
2
LVCMOS
Qx
V
DD
x
2
tsk(o)
Qy
GND = -1.65V±0.15V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
PART 1
Qx
V
DD
x
2.0V
2.0V
V
SW I N G
2
0.8V
Clock Outputs
PART 2
Qy
0.8V
t
R
V
DD
x
t
F
2
tsk(pp)
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
CLK0,
CLK1
V
DD
2
QAx, QBx,
QCx, QDx
V
DD
x
2
t
PD
Propagation Delay
87946AYI
www.icst.com/products/hiperclocks.html
5
REV. B OCTOBER 27, 2008
微控制器 MCU
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