Low Voltage, LVCMOS/LVPECL-to-LVPECL/ECL
Clock Generator
G
ENERAL
D
ESCRIPTION
The 873991-147 is a low voltage, low skew, 3.3V LVPECL or ECL
Clock Generator and a member of the family of High Performance
Clock Solutions from IDT. The 873991-147 has two selectable clock
inputs. The CLK, nCLK pair can accept LVPECL, LVDS, LVHSTL,
SSTL and HCSL input levels and, the REF_CLK pin can accept a
LVCMOS or LVTTL input levels. This device has a fully integrated
PLL along with frequency configurable outputs. An external feedback
input and output regenerates clocks with “zero delay”.
The four independent banks of outputs each have their own output
dividers, which allow the device to generate a multitude of differ-
ent bank frequency ratios and output-to-input frequency ratios.
The output frequency range is 25MHz to 480MHz and the input
frequency range is 6.25MHz to 120MHz. The PLL_EN input can
be used to bypass the PLL for test and system debug purposes.
In bypass mode, the input clock is routed around the PLL and into
the internal output dividers.
The 873991-147 also has a SYNC output which can be used for
system synchronization purposes. It monitors Bank A and Bank
C outputs for coincident rising edges and signals a pulse per the
timing diagrams in this data sheet. This feature is used primarily
in applications where Bank A and Bank C are running at different
frequencies, and is particularly useful when they are running at
non-integer multiples of each other.
Example Applications:
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane
to 77.76MHz on the line card ASIC and Serdes.
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies
from a reference clock to multiple processing units on an
embedded system.
843N001I
DATASHEET
F
EATURES
•
Fourteen differential 3.3V LVPECL/ECL outputs
•
Selectable differential or REF_CLK inputs
•
CLK, nCLK can accept the following input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
REF_CLK accepts the following input levels: LVCMOS, LVTTL
•
Input clock frequency range: 6.25MHz to 120MHz
•
Maximum output frequency: 480MHz
•
VCO range: 200MHz to 960MHz
•
Output skew: 250ps (maximum), outputs at the same frequency
•
Cycle-to-cycle jitter: 55ps (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3.135V to 3.465V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -3.135V
•
0°C to 50°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
Use replacement part 873996AYLF
P
IN
A
SSIGNMENT
873991-147 REVISION B 8/25/15
1
©2015 Integrated Device Technology, Inc.
873991-147 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
Name
V
EE
MR
Power
Input
Type
Description
Negative supply pin.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inverted outputs
Pulldown
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, PLL
Pulldown
is in bypass mode. LVCMOS/LVTTL interface levels.
Selects between the different reference inputs as the PLL reference
Pulldown source. When logic LOW, selects CLK/nCLK. When logic HIGH, selects
REF_CLK. LVCMOS/LVTTL interface levels.
Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input. V
CC
/2 default when left floating.
Pulldown
Core supply pin.
Pulldown Non-inverting external feedback input.
Pullup/
Inverting external feedback input. V
CC
/2 default when left floating.
Pulldown
Analog supply pin.
Differential feedback output pair. LVPECL Interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
SYNC output select pin. When LOW, the SYNC otuput follows the timing
Pulldown diagram (page 5). When HIGH, QD output follows QC output LVCMOS/
LVTTL interface levels..
Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17, 22, 30, 42
18, 19
20, 21
23, 24
25, 26
27
33
36
39
28, 29
31, 32
34, 35
37, 38
40, 41
43, 44
45, 46
47, 48
49, 50
51
52
PLL_EN
REF_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
REF_CLK
CLK
nCLK
V
CC
EXT_FB
nEXT_FB
V
CCA
nQFB
QFB
V
CCO
nQD0, QD0
nQD1, QD1
nQC0, QC0
nQC1, QC1
FSEL3
FSEL2
FSEL1
FSEL0
nQC2, QC2
nQB0, QB0
nQB1, QB1
nQB2, QB2
nQB3, QB3
nQA0, QA0
nQA1, QA1
nQA2, QA2
nQA3, QA3
SYNC_SEL
VCO_SEL
Input
Input
Input
Input
Input
Input
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 8/25/15
3
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL
CLOCK GENERATOR
为我们提建议&公告
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
