DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889875
Features
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Two LVDS outputs
Frequency divide select options: ÷1, ÷2, ÷4, ÷8, ÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: >2GHz
Cycle-to-cycle jitter: 1ps RMS (maximum)
Total jitter: 10ps (typical)
Output skew: 15ps (maximum)
Part-to-part skew: 280ps (maximum)
Propagation Delay: 1140ps (maximum)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS889875 is a high speed Differential-to-
LVDS Buffer/Divider w/Internal Termination and is a
HiPerClockS™
member of the HiPerClockS™ family of high
performance clock solutions from IDT. The
ICS889875 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16
output dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
ICS
Block Diagram
S2
Pullup
Pin Assignment
GND
V
DD
S0
S1
Q0 1
nRESET/
nDISABLE
Pullup
Enable
FF
nQ0
2
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
6
nc
Q1 3
nQ1 4
7
V
DD
8
nRESET/
nDISABLE
V
REF_AC
Enable
MUX
Q0
MUX
nQ0
IN
50Ω
ICS889875
50Ω
V
T
nIN
÷2, ÷4,
÷8, ÷16
Q1
nQ1
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
S1
Pullup
Decoder
S0
Pullup
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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ICS889875
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
Output
Type
Description
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be
terminated with 100
Ω
across the differential pair.
LVDS interface levels.
Differential output pair. Divide by 1, 2, 4, 8, or 16. Unused outputs must be
terminated with 100
Ω
across the differential pair.
LVDS interface levels.
Pullup
Select pins. Internal 37k
Ω
pullup resistor. Logic HIGH if left disconnected.
Input threshold is V
DD
/2. LVCMOS/LVTTL interface levels.
No connect.
Power supply pins.
Synchronizing enable/disable pin. When LOW, resets the divider (divided by
1, 2, 4, 8 or 16 mode). When HIGH, disconnected. The reset and disable
function occurs on the next high-to-low clock input transition.
Input threshold is V
DD
/2V. Includes a 37k
Ω
pull-up resistor.
LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. R
T
= 50
Ω
termination to V
T
.
Reference voltage for AC-coupled applications. Equal to V
DD
– 1.4V
(approx.). Maximum sink/source current is 0.5mA.
Termination center-tap input.
Non-inverting LVPECL differential clock input.
R
T
= 50
Ω
termination to V
T
.
Power supply ground.
3, 4
Q1, nQ1
Output
5, 15, 16
6
7, 14
S2, S1, S0
nc
V
DD
Input
Unused
Power
8
nRESET/
nDISABLE
Input
Pullup
9
10
11
12
13
nIN
V
REF_AC
V
T
IN
GND
Input
Output
Input
Input
Power
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
Ω
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Function Tables
Table 3A. Control Input Function Table
Input
nRESET
0
1
Q0, Q1
Disabled; LOW
Enabled
Outputs
nQ0, nQ1
Disabled; HIGH
Enabled
NOTE: After nRESET switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in
Figure 1.
Figure 1. nRESET Timing Diagram
V
DD
/2
nRESET
nIN
IN
V
IN
Swing
nQx
Qx
V
OUT
Swing
t
PD
t
RR
Table 3B. Truth Table
Inputs
nRESET/nDISABLE
1
1
1
1
1
0 (NOTE 1)
S2
0
1
1
1
1
X
S1
X
0
0
1
1
X
S0
X
0
1
0
1
X
Outputs
Q0/nQ0, Q1/nQ1
Reference Clock (pass through)
Reference Clock ÷2
Reference Clock ÷4
Reference Clock ÷8
Reference Clock ÷16
Qx = LOW, nQx = HIGH; Clock disabled
NOTE 1: Reset/disable function is asserted on the next clock input (IN/nIN) high-to-low transition.
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
± 0.5mA
-40°C to +85°C
88.5°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
82
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
2
0
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
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DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Table 4C. Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current
Bias Voltage
(IN, nIN)
V
DD
– 1.35
(IN, nIN)
(IN, nIN)
(IN, nIN)
1.2
0
0.15
0.3
45
Test Conditions
Minimum
Typical
100
V
DD
+ 0.05
V
DD
– 0.15
2.8
Maximum
Units
Ω
V
V
V
V
mA
V
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OUT
V
OH
V
OL
V
CCM
∆V
OCM
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
0.925
1.35
50
Test Conditions
Minimum
250
Typical
350
1.475
Maximum
400
Units
mV
V
V
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit(cc)
tjit(j)
t
RR
t
R
/ t
F
Symbol
Maximum Input Frequency
Propagation Delay;
NOTE 1
IN-to-Q
Test Conditions
÷1, ÷2, ÷4
÷8, ÷16
690
Minimum
Typical
>2
>1.5
1140
15
280
1
10
600
70
260
Maximum
Units
GHz
GHz
ps
ps
ps
ps
ps
ps
ps
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Cycle-to-Cycle Jitter, RMS; NOTE 5
Total Jitter
Reset Recovery Time
Output Rise/Fall Time
All parameters characterized at f
MAX
unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
IDT™ / ICS™
LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
5
ICS889875AK REV. B OCTOBER 27, 2008
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