ICS85210-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS85210-21 is a low skew, high performance dual
1 - t o -5 Differential-to-HSTL F a n o u t B u f f e r . The CLKx,
nCLKx pairs can accept most standard differential input
levels. The ICS85210-21 is characterized to operate
from a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85210-
21 i d e a l f o r t h o s e c l o c k d i s t r i b u t i o n a p p l i c a t i o n s
demanding well defined performance and
repeatability.
F
EATURES
•
Dual 1-to-5 HSTL bank outputs
•
2 selectable differential clock input pairs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
•
Maximum output frequency: 650MHz
•
Translates any single ended input signal to 3.3V
HSTL levels with resistor bias on nCLKx inputs
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 350ps (maximum)
•
Propagation delay: 2ns (maximum)
•
3.3V core, 1.8V output operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
CLK0
nCLK0
QA0
nQA0
P
IN
A
SSIGNMENT
nQA0
nQA1
nQA2
V
DDO
V
DDO
QA1
nQA1
QA2
nQA2
V
DD
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
nc
CLK0
nCLK0
nc
CLK1
nCLK1
GND
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
ICS85210-21
QA0
QA1
QA2
21
20
19
18
17
CLK1
nCLK1
9 10 11 12 13 14 15 16
V
DDO
nQB4
QB4
nQB3
QB3
nQB2
QB2
V
DDO
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
85210AY-21
www.idt.com
1
REV. B JULY 25, 2010
ICS85210-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 5
3
4
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
DD
nc
CLK0
nCLK0
CLK1
nCLK1
GND
V
DDO
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Power
Unused
Input
Input
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pullup
Type
Description
Core supply pin.
No connect.
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Inver ting differential clock input.
Power supply ground.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Pulldown Non-inver ting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
85210AY-21
www.idt.com
2
REV. B JULY 25, 2010
ICS85210-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Input Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
120
Units
V
V
mA
mA
T
ABLE
3B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLKx and nCLKx is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
3C. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
Output High Voltage;
V
OH
NOTE 1
Output Low Voltage;
V
OL
NOTE 1
V
OX
V
SWING
Output Crossover Voltage
Test Conditions
Minimum
1
0
40% x (V
OH
- V
OL
) + V
OL
0.6
Typical
Maximum
1.4
0.4
60% x (V
OH
- V
OL
) + V
OL
1.1
Units
V
V
V
V
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
85210AY-21
www.idt.com
3
REV. B JULY 25, 2010
ICS85210-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
30% to 70% @ 50MHz
300
IJ 650MHz
1.5
Test Conditions
Minimum
Typical
Maximum
650
2
50
350
700
53
Units
MHz
ns
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
47
All parameters measured at 400MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85210AY-21
www.idt.com
4
REV. B JULY 25, 2010
ICS85210-21
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V±5%
V
DD
Qx
SCOPE
V
DD
HSTL
nQx
nCLK0,
nCLK1
V
PP
Cross Points
V
CMR
GND
CLK0,
CLK1
GND
0V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
Qx
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
Qx
PART 1
nQx
Qy
PART 2
nQy
t
sk(o)
t
sk(pp)
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
nCLK0,
nCLK1
70%
Clock
Outputs
70%
V
SW I N G
30%
t
R
t
F
30%
CLK0,
CLK1
nQAx,
nQBx
QAx,
QBx
t
PD
O
UTPUT
R
ISE
/F
ALL
T
IME
nQAx,
nQBx
QAx,
QBx
P
ROPAGATION
D
ELAY
Pulse Width
t
PERIOD
odc =
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
85210AY-21
www.idt.com
5
REV. B JULY 25, 2010
嵌入式系统
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