DATA SHEET
Integrated
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V
Circuit
L
OW
S
KEW
, 1-
TO
-6
LVPECL/ECL
Systems, Inc.
BUFFER
FANOUT
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
ICS853006
G
ENERAL
D
ESCRIPTION
The ICS853006 is a low skew, high performance
1-to-6 Differential-to-2.5V/3.3V LVPECL/ECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClock ™
S
family of High Performance Clock Solutions from
ICS. The ICS853006 is characterized to operate
from a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853006 ideal
for those applications demanding well defined performance
and repeatability.
F
EATURES
•
6 differential LVPECL outputs
•
1 differential PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: > 2GHz
•
Output skew: 30ps (maximum)
•
Part-to-part skew: 150ps (maximum)
•
Propagation delay: 510ps (maximum)
•
Jitter, RMS: < 0.03ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.465V
•
Lead-Free package available
•
-40°C to 85°C ambient operating temperature
ICS
B
LOCK
D
IAGRAM
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
P
IN
A
SSIGNMENT
V
CC
nQ0
Q0
nQ1
Q1
nQ2
Q2
V
CC
PCLK
nPCLK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q5
nQ5
Q4
nQ4
Q3
nQ3
VCC
V
EE
V
BB
V
BB
ICS853006
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
853006AG
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 9, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
1
ICS853006
Integrated
ICS853006
Circuit
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Systems, Inc.
ICS853006
L
OW
S
KEW
, 1-
TO
-6
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
Description
Positive supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup/
Inver ting differential LVPECL clock input. V
CC
/2 default when left floating.
Pulldown
Bias voltage.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 8, 13, 20
2, 3
4, 5
6, 7
9
10
11
12
14, 15
16, 17
Name
V
CC
nQ0, Q0
nQ1, Q1
nQ2, Q2
PCLK
nPCLK
V
BB
V
EE
nQ3, Q3
nQ4, Q4
Power
Output
Output
Output
Input
Input
Output
Power
Output
Output
Type
18, 19
nQ5, Q5
Output
Differential output pair. LVPECL interface levels.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Input Pulldown Resistor
Input Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
75
50
Maximum
Units
KΩ
KΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Input
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
Q0:Q5
nQ0:nQ5
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853006AG
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 9, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
2
ICS853006
Integrated
ICS853006
Circuit
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Systems, Inc.
ICS853006
L
OW
S
KEW
, 1-
TO
-6
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, V
CC
= 0)
to the device. These ratings are stress specifi-
-0.5V to V + 0.5 V
CC
0.5V to V
EE
- 0.5V
50mA
100mA
± 0.5mA
-65°C to 150°C
73.2°C/W (0 lfpm)
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.465V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.465
115
Units
V
mA
T
ABLE
4B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK, nPCLK
High Current
PCLK
Input
Low Current nPCLK
Min
2.175
1.405
2.075
1.43
1.86
150
1.2
800
-40°C
Typ
2.275
1.545
Max
2.38
1.68
2.36
1.765
1.98
1200
3.3
150
Min
2.225
1.425
2.075
1.43
1.86
150
1.2
25°C
Typ
2.295
1.52
Max
2.37
1.615
2.36
1.765
1.98
Min
2.295
1.44
2.075
1.43
1.86
150
1.2
85°C
Typ
2.33
1.535
Max
2.365
1.63
2.36
1.765
1.98
Units
V
V
V
V
V
800
1200
3.3
150
800
1200
3.3
150
m
V
V
µA
µA
µA
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
853006AG
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 9, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3
ICS853006
Integrated
ICS853006
Circuit
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Systems, Inc.
ICS853006
L
OW
S
KEW
, 1-
TO
-6
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
-40°C
Min
1.375
0.605
1.275
0.63
150
1.2
800
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, nPCLK
High Current
Input
Low Current
PCLK
25°C
Max
1.58
0.88
1.56
0.965
1200
2.5
150
-10
-10
85°C
Max
1.57
0.815
1.56
0.965
Typ
1.475
0.745
Min
1.425
0.625
1.275
0.63
150
1.2
Typ
1.495
0.72
Min
1.495
0.64
1.275
0.63
150
1.2
Typ
1.53
0.735
Max
1.565
0.83
Units
V
V
V
V
-0.83
0.965
800
1200
2.5
150
800
1200
2.5
150
m
V
V
µA
µA
µA
-10
-150
-150
-150
nPCLK
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
T
ABLE
4D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.465V
TO
-2.375V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage
(Single-Ended)
Input Low Voltage
(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK, nPCLK
High Current
Input
Low Current
PCLK
-40°C
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
V
EE
+1.2V
800
25°C
Max
-0.92
-1.62
-0.94
-1.535
-1.32
1200
0
150
85°C
Max
-0.93
-1.685
-0.94
-1.535
-1.32
Typ
-1.025
-1.755
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
V
EE
+1.2V
Typ
-1.005
-1.78
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
V
EE
+1.2V
Typ
-0.97
-1.765
Max
-0.935
-1.67
-0.94
-1.535
-1.32
Units
V
V
V
V
V
800
1200
0
150
800
1200
0
150
m
V
V
µA
µA
µA
-10
-10
-10
-150
-150
-150
nPCLK
Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
853006AG
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 9, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
4
ICS853006
Integrated
ICS853006
Circuit
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Systems, Inc.
ICS853006
L
OW
S
KEW
, 1-
TO
-6
TSD
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
-40°C
Min
340
Typ
>2
400
15
460
27
150
0.03
95
150
205
95
0.03
150
205
95
350
Max
Min
25°C
Typ
>2
410
15
470
27
150
0.03
150
205
390
Max
Min
85°C
Typ
>2
450
17
510
30
150
Max
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -2.375V
TO
-3.465V
OR
V
CC
= 2.375
TO
3.465V; V
EE
= 0V
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
20% to 80%
Units
GHz
ps
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
All parameters are measured
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853006AG
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 9, 2004
IDT™ / ICS™
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
5
ICS853006
嵌入式系统
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