DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ICS889831
General Description
The ICS889831 is a high speed 1-to-4 Differential-
to-LVPECL/ECL Fanout Buffer and is a member of
HiPerClockS™
the HiPerClockS™ family of high performance clock
solutions from IDT. The ICS889831 is optimized for
high speed and very low output skew, making it
suitable for use in demanding applications such as SONET, 1
Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally
terminated differential input and V
REF
_
AC
pin allow other
differential signal families such as LVDS, LVHSTL and CML to be
easily interfaced to the input with minimal use of external
components. The device also has an output enable pin which may
be useful for system test and debug purposes. The ICS889831 is
packaged in a small 3mm x 3mm 16-pin VFQFN package which
makes it ideal for use in space-constrained applications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Four LVPECL/ECL outputs
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
50
Ω
internal input termination to V
T
Output frequency: >2.1GHz
Output skew: 30ps (maximum)
Part-to-part skew: 185ps (maximum)
Additive phase jitter, RMS: 0.27ps (typical)
Propagation Delay: 570ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.5V±5%, 3.3V±5%, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.3V±5%, 2.5V±5%
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
EN
D
Q
Q0
nQ0
Q1
50Ω
50Ω
Pin Assignment
nQ0
V
CC
Q1 1
nQ1
2
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
Q3
IN
V
T
nIN
V
REF_AC
Q2 3
nQ1
nQ2 4
6
nQ3
7
V
CC
nQ2
ICS889831
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
Q3
nQ3
IDT™ / ICS™
LVPECL/ECL FANOUT BUFFER
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ICS889831AK REV. B OCTOBER 21 , 2008
EN
Q2
V
EE
Q0
8
ICS889831
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 14
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
V
cc
Output
Output
Output
Power
Type
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Power supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ
outputs will go HIGH on the next LOW transition at IN inputs. Input threshold
is VCC/2V. Includes a 37kW pull-up resistor. Default state is HIGH when left
floating. The internal latch is clocked on the falling edge of the input signal IN.
LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50
Ω
termination to V
T
.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting LVPECL differential clock input.
RT = 50
Ω
termination to V
T
.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
8
EN
Input
Pullup
9
10
11
12
13
15, 16
nIN
V
REF_AC
V
T
IN
V
EE
Q0, nQ0
Input
Output
Input
Input
Power
Output
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
Ω
IDT™ / ICS™
LVPECL/ECL FANOUT BUFFER
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ICS889831
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Input
EN
0
1
Q0:Q3
Disabled; LOW
Enabled
Outputs
nQ0:nQ3
Disabled; HIGH
Enabled
NOTE: After EN switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in
Figure 1.
EN
V
CC
/2
t
S
nIN
IN
V
CC
/2
t
H
V
IN
nQx
Qx
→
t
PD
←
V
OUT
Swing
Figure 1. EN Timing Diagram
Table 3B. Truth Table
Inputs
IN
0
1
X
nIN
1
0
X
EN
1
1
0
Q0:Q3
0
1
0 (NOTE1)
Outputs
nQ0:nQ3
1
0
1(NOTE1)
NOTE 1: On the next negative transition of the input signal (IN).
IDT™ / ICS™
LVPECL/ECL FANOUT BUFFER
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ICS889831AK REV. B OCTOBER 21 , 2008
ICS889831
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuos Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
±50mA
±100mA
± 0.5mA
-40°C to +85°C
51.5°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.465
60
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 2.5V ± 5%, 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
0
Typical
Maximum
V
CC
+ 0.3
0.8
5
Units
V
V
µA
µA
IDT™ / ICS™
LVPECL/ECL FANOUT BUFFER
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ICS889831AK REV. B OCTOBER 21 , 2008
ICS889831
DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Table 4C. Differential DC Characteristics,
V
CC
= 2.5V ± 5%, 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current; NOTE 1
Bias Voltage
(IN, nIN)
V
CC
– 1.42
V
CC
– 1.37
(IN, nIN)
(IN, nIN)
(IN, nIN)
Test Conditions
Minimum
40
1.2
0
0.15
0.3
Typical
50
Maximum
60
V
CC
V
IH
– 0.15
2.8
3.4
35
V
CC
– 1.32
Units
Ω
V
V
V
V
mA
V
NOTE 1: Guaranteed by design.
Table 4D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OUT
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.125
V
CC
– 1.89525
0.6
1.2
Typical
V
CC
– 1.005
V
CC
– 1.78
Maximum
V
CC
– 0.935
V
CC
– 1.67
1.0
2.0
Units
V
V
V
V
V
DIFF_OUT
Differential Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
– 2V.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 0V; V
EE
= -3.3V ± 5%, -2.5V ± 5% or V
CC
= 2.5V ± 5%, 3.3V ± 5%, V
EE
= 0V,
T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
S
t
H
t
R
/ t
F
Symbol
Output Frequency
Propagation Delay; (Differential);
NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Jitter; RMS; refer
to Additive Phase Jitter Section
Clock Enable
Setup Time
Clock Enable
Hold Time
EN to IN/nIN
EN to IN/nIN
20% to 80%
Integration Range:
12kHz – 20MHz
300
300
100
250
0.27
Test Conditions
Output Swing
≥
450mV
Input Swing: 100mV
Input Swing: 800mV
Minimum
2.1
300
255
435
370
570
485
30
185
1
Typical
Maximum
Units
GHz
ps
ps
ps
ps
ps
ps
ps
ps
Output Rise/Fall Time
All parameters characterized at
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™
LVPECL/ECL FANOUT BUFFER
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ICS889831AK REV. B OCTOBER 21 , 2008