FEATURES
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LTC3731
3-Phase, 600kHz,
Synchronous Buck Switching
Regulator Controller
DESCRIPTIO
The LTC
®
3731 is a PolyPhase
®
synchronous step-down
switching regulator controller that drives all N-channel ex-
ternal power MOSFET stages in a phase-lockable fixed fre-
quency architecture. The 3-phase controller drives its
output stages with 120° phase separation at frequencies of
up to 600kHz per phase to minimize the RMS current losses
in both the input and output filter capacitors. The 3-phase
technique effectively triples the fundamental frequency,
improving transient response while operating each control-
ler at an optimal frequency for efficiency and ease of ther-
mal design. Light load efficiency is optimized by using a
choice of output Stage Shedding or Burst Mode operation.
A differential amplifier provides true remote sensing of both
the high and low side of the output voltage at the point of
load. The precision reference supports output voltages from
0.6V to 6V.
Soft-start and a defeatable, timed short-circuit shutdown
protect the MOSFETs and the load. Current foldback
provides protection for the external MOSFETs under
short-circuit or overload conditions.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology
Corporation. Stage Shedding is a trademark of Linear Technology Corporation.
*Protected by U.S. Patents including 5481178, 5929620, 6177787, 6144194, 6100678,
5408150, 6580258, 6462525, 6304066, 5705919.
3-Phase Current Mode Controller with Onboard
MOSFET Drivers
±5%
Output Current Matching Optimizes Thermal
Performance and Size of Inductors and MOSFETs
Differential Amplifier Accurately Senses V
OUT
±1%
V
REF
Accuracy Over Temperature
Reduced Power Supply Induced Noise
±10%
Power Good Output Indicator
250kHz to 600kHz Per Phase, PLL, Fixed Frequency
PWM, Stage Shedding
TM
or Burst Mode
®
Operation
OPTI-LOOP
®
Compensation Minimizes C
OUT
Adjustable Soft-Start Current Ramping
Short-Circuit Shutdown Timer with Defeat Option
Overvoltage Soft Latch
Adjustable Undervoltage Lockout Threshold
Selectable Phase Output for Up to 12-Phase Operation
Available in 5mm
×
5mm QFN and 36-Pin Narrow
(0.209") SSOP Packages
APPLICATIO S
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Desktop Computers and Servers
High Performance Notebook Computers
High Output Current DC/DC Power Supplies
TYPICAL APPLICATIO
V
CC
4.5V TO 7V
V
CC
10µF
LTC3731
BOOST1
BOOST2
BOOST3
0.1µF
SW3 SW2 SW1
TG1
SW1
BG1
SENSE1
+
SENSE1
–
TG2
SW2
BG2
PGND
SENSE2
+
SENSE2
–
TG3
SW3
BG3
SENSE3
+
SENSE3
–
V
IN
V
IN
0.8µH
0.003Ω
POWER GOOD INDICATOR
OPTIONAL SYNC IN
PGOOD
PLLIN
PLLFLTR
0.8µH
0.003Ω
36k
V
IN
12k
680pF
I
TH
5k
0.01µF
100pF
7.5k
6.04k
RUN/SS
SGND
EAIN
DIFFOUT
IN
–
IN
+
UVADJ
0.8µH
0.003Ω
Figure 1. High Current Triple Phase Step-Down Converter
3731fa
U
U
U
+
V
IN
5V TO 28V
22µF
35V
V
OUT
1.35V
55A
+
C
OUT
470µF
4V
3731 F01
1
LTC3731
ABSOLUTE
AXI U
RATI GS
Topside Driver Voltages (BOOST
N
) ............ 38V to –0.3V
Switch Voltage (SW
N
)................................... 32V to –5V
Boosted Driver Voltage (BOOST
N
– SW
N
) .... 7V to –0.3V
Peak Output Current <1ms (TG
N
, BG
N
) ..................... 5A
Supply Voltages (V
CC
, V
DR
), PGOOD
Pin Voltage .................................................. 7V to –0.3V
RUN/SS, PLLFLTR, PLLIN, UVADJ,
FCB Voltages ............................................. V
CC
to –0.3V
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V
CC
PLLIN
PLLFLTR
FCB
IN
+
IN
–
DIFFOUT
EAIN
SGND
SENSE1
–
SENSE2
+
SENSE2
–
SENSE3
–
1
2
3
4
5
6
7
8
9
36 CLKOUT
35 PGOOD
34 BOOST1
33 TG1
32 SW1
31 BOOST2
30 TG2
29 SW2
28 V
DR
27 BG1
26 PGND
25 BG2
24 BG3
23 SW3
22 TG3
21 BOOST3
20 PHASMD
19 SGND2
PLLFLTR
CLKOUT
BOOST1
ORDER PART
NUMBER
LTC3731CG
LTC3731IG
IN
–
1
DIFFOUT 2
EAIN 3
SENSE1
+
4
SENSE1
–
SENSE2
+
SENSE2
–
5
6
7
FCB
IN
+
PLLIN
SW1
32 31 30 29 28 27 26 25
24 BOOST2
23 TG2
22 SW2
33
21 V
CC
20 BG1
19 PGND
18 BG2
17 BG3
9 10 11 12 13 14 15 16
SENSE3
+
UVADJ
PHASMD/PG
BOOST3
TG3
RUN/SS
SW3
I
TH
TG1
SENSE1
+
10
11
12
13
14
SENSE3
+
15
RUN/SS 16
I
TH
17
UVADJ 18
G PACKAGE
36-LEAD PLASTIC SSOP
T
JMAX
= 125°C,
θ
JA
= 95°C/W,
θ
JC
= 32°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL
V
REGULATED
PARAMETER
Regulated Voltage at IN
+
Main Control Loop
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= V
RUN/SS
= 5V unless otherwise noted.
CONDITIONS
V
ITH
= 1.2V (Note 3)
LTC3731IG
●
●
2
U
U
W
W W
U
W
(Note 1)
I
TH
Voltage ................................................ 2.4V to –0.3V
Operating Ambient Temperature Range
LTC3731C .................................................... 0°C to 70°C
LTC3731I ................................................. –40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature G Package (Soldering, 10sec).. 300°C
Peak Body Temperature UH Package ................... 240°C
ORDER PART
NUMBER
LTC3731CUH
LTC3731IUH
UH PART
NUMBER
3731
3731I
SENSE3
–
8
UH PACKAGE
32-LEAD PLASTIC QFN
EXPOSED PAD (PIN 33) IS SIGNAL GROUND
(SGND) AND MUST BE SOLDERED TO PCB
T
JMAX
= 125°C,
θ
JA
= 34°C/W
MIN
0.596
0.594
0.591
TYP
0.600
0.600
MAX
0.604
0.606
0.609
UNITS
V
V
V
3731fa
LTC3731
ELECTRICAL CHARACTERISTICS
SYMBOL
V
SENSEMAX
PARAMETER
Maximum Current Sense Threshold
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= V
RUN/SS
= 5V unless otherwise noted.
CONDITIONS
V
EAIN
= 0.5V, V
ITH
Open,
V
SENSE1
–
,
V
SENSE2
–
,
V
SENSE3
– = 0.6V, 1.8V
LTC3731IG
Worst-Case Error at V
SENSEMAX
(Note 3)
Measured in Servo Loop,
∆I
TH
Voltage = 1.2V to 0.7V
LTC3731IG
Measured in Servo Loop,
∆I
TH
Voltage = 1.2V to 2V
LTC3731IG
V
CC
= 4.5V to 7V
I
TH
= 1.2V, Sink/Source 25µA (Note 3)
LTC3731IG
I
TH
= 1.2V (g
m
• Z
L
, Z
L
= Series 1k-100kΩ-1nF)
LTC3731IG
●
●
●
●
●
●
●
●
●
●
MIN
65
62
60
–5
TYP
75
75
MAX
85
88
90
5
UNITS
mV
mV
mV
%
%
%
%
%
%/V
mmho
mmho
MHz
V
V
µA
V
V
V
nA
mA
µA
µA
V
V
V
µA
I
MATCH
V
LOADREG
Maximum Current Threshold Match
Output Voltage Load Regulation
0.1
0.1
–0.1
–0.1
0.03
4
3
0.58
0.54
5
5
3
0.60
0.60
0.2
0.5
0.7
–0.5
–0.7
6
7
0.62
0.66
0.7
V
REFLNREG
g
m
g
mOL
V
FCB
I
FCB
V
BINHIBIT
UVR
UVADJ
I
UVADJ
I
Q
Output Voltage Line Regulation
Transconductance Amplifier g
m
Transconductance Amplifier GBW
Forced Continuous Threshold
FCB Bias Current
Burst Inhibit Threshold
Undervoltage RUN/SS Reset
Undervoltage Lockout Threshold
Undervoltage Bias Current
Input DC Supply Current
Normal Mode
Shutdown
Soft-Start Charge Current
RUN/SS Pin ON Threshold
V
FCB
= 0.65V
Measured at FCB Pin
V
CC
Lowered Until the RUN/SS Pin is Pulled Low
At UVADJ Threshold
(Note 4)
V
CC
= 5V
V
RUN/SS
= 0V
V
RUN/SS
= 1.9V
V
RUN/SS
, Ramping Positive
V
RUN/SS
, Ramping Positive Until Short-Circuit
Latch-Off is Armed
V
RUN/SS
, Ramping Negative
Soft-Short Condition V
EAIN
= 0.375V, V
RUN/SS
= 4.5V
V
EAIN
= 0.375V, V
RUN/SS
= 4.5V
SENSE1
+
, SENSE1
–
, SENSE2
+
, SENSE2
–
, SENSE3
+
SENSE3
–
All Equal 1.2V; Current at Each Pin
In Dropout, V
SENSEMAX
≤
30mV
C
LOAD
= 3300pF
C
LOAD
= 3300pF
C
LOAD
= 3300pF
C
LOAD
= 3300pF
All Controllers, C
LOAD
= 3300pF Each Driver
All Controllers, C
LOAD
= 3300pF Each Driver
Tested with a Square Wave (Note 5)
95
–5
–0.8
1
V
CC
– 1.5 V
CC
– 0.7 V
CC
– 0.3
3.3
3.8
4.5
1.13
1.18
0.2
2.3
50
–1.5
1.5
3.8
3.2
–1.5
1.5
13
98.5
30
40
30
20
50
60
110
90
90
90
90
5
20
1.23
50
3.5
100
– 2.5
1.9
4.5
I
RUN/SS
V
RUN/SS
V
RUN/SSARM
RUN/SS Pin Arming Threshold
V
RUN/SSLO
I
SCL
I
SDLHO
I
SENSE
DF
MAX
TG t
R,
t
F
BG t
R,
t
F
TG/BG t
1D
BG/TG t
2D
t
ON(MIN)
RUN/SS Pin Latch-Off Threshold
RUN/SS Discharge Current
Shutdown Latch Disable Current
SENSE Pins Source Current
Maximum Duty Factor
Top Gate Rise Time
Top Gate Fall Time
Bottom Gate Rise Time
Bottom Gate Fall Time
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
Minimum On-Time
µA
µA
%
ns
ns
ns
ns
ns
ns
ns
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LTC3731
ELECTRICAL CHARACTERISTICS
SYMBOL
V
PGL
I
PGOOD
I
PGOOD
V
PGTHNEG
V
PGTHPOS
V
PGDLY
f
NOM
f
LOW
f
HIGH
V
PLLTH
R
PLLIN
I
PLLFLTR
PARAMETER
PGOOD Voltage Output Low
PGOOD Output Leakage
PGOOD/PHASMD Bias I
PGOOD Trip Thesholds
V
DIFFOUT
Ramping Negative
V
DIFFOUT
Ramping Positive
Power Good Fault Report Delay
Nominal Frequency
Lowest Frequency
Highest Frequency
PLLIN Input Threshold
PLLIN Input Resistance
Phase Detector Output Current
Sinking Capability
Sourcing Capability
Controller 2-Controller 1 Phase
Controller 3-Controller 1 Phase
Controller 1 TG to CLKOUT Phase
PHASMD = 0V
PHASMD = 5V
0.995
IN
+
= IN
–
= 1.2V, I
OUT
= 1mA,
Input Referred; Gain = 1
0
0V < IN
+
= IN
–
< 5V, I
OUT
= 1mA, Input Referred
I
OUT
= 1mA
R
L
= 2k
I
OUT
= 1mA
Measured at IN
+
Pin
50
10
70
40
2
5
V
CC
– 1.2 V
CC
– 0.8
80
f
PLLIN
< f
OSC
f
PLLIN
> f
OSC
Power Good Output Indication
I
PGOOD
= 2mA, G Package
I
PGOOD
= 1.6mA, UH Package
V
PGOOD
= 5V, G Package
0
≤
V
PHASMD/PG
≤
V
CC
, UH Package
V
DIFFOUT
with Respect to Set Output Voltage,
HGOOD Goes Low After V
UVDLY
Delay
After V
EAIN
is Forced Outside the PGOOD Thresholds
V
PLLFLTR
= 1.2V
V
PLLFLTR
= 0V
V
PLLFLTR
= 2.4V
Minimum Pulse Width > 100ns
360
190
600
–10
–7
7
±3
–10
10
100
400
225
680
1
50
20
20
120
240
30
60
1.000
0.5
1.005
5
V
CC
0.1
0.5
0.3
1.0
1
10
–13
13
150
440
260
750
V
V
µA
µA
%
%
µs
kHz
kHz
kHz
V
kΩ
µA
µA
Deg
Deg
Deg
Deg
V/V
mV
V
dB
mA
MHz
V/µs
V
kΩ
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= V
RUN/SS
= 5V unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
R
RELPHS
CLKOUT
Differential Amplifier
A
V
V
OS
CM
CMRR
I
CL
GBP
SR
V
O(MAX)
R
IN
Differential Gain
Input Offset Voltage Magnitude
Common Mode Input Voltage Range
Common Mode Rejection Ratio
Output Current Sourcing
Gain Bandwidth Product
Slew Rate
Maximum High Output Voltage
Input Resistance
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC3731CG/LTC3731IG: T
J
= T
A
+ (P
D
×
95°C/W)
LTC3731CG/LTC3731IG: T
J
= T
CASE
+ (P
D
×
32°C/W)
LTC3731CUH/LTC3731IUH: T
J
= T
A
+ (P
D
×
34°C/W)
Note 3:
The IC is tested in a feedback loop that includes the differential
amplifier loaded with 100µA to ground driving the error amplifier and
servoing the resultant voltage to the midrange point for the error amplifier
(V
ITH
= 1.2V).
Note 4:
Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5:
The minimum on-time condition corresponds to an inductor peak-
to-peak ripple current of
≥
40% of I
MAX
(see minimum on-time
considerations in the Applications Information Section).
Note 6:
This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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LTC3731
PI FU CTIO S
BG1 to BG3:
High Current Gate Drives for Bottom N-Channel
MOSFETs. Voltage swing at these pins is from ground to V
CC
.
BOOST1 to BOOST3:
Positive Supply Pins to the Topside
Floating Drivers. Bootstrapped capacitors, charged with exter-
nal Schottky diodes and a boost voltage source, are connected
between the BOOST and SW pins. Voltage swing at the BOOST
pins is from boost source voltage (typically V
CC
) to this boost
source voltage + V
IN
(where V
IN
is the external MOSFET supply
rail).
CLKOUT:
Output clock signal available to synchronize other
controller ICs for additional MOSFET stages/phases.
DIFFOUT:
Output of the Remote Output Voltage Sensing
Differential Amplifier.
EAIN:
This is the input to the error amplifier that compares the
feedback voltage to the internal 0.6V reference voltage.
FCB:
Forced Continuous Control Input. The voltage applied to
this pin sets the operating mode of the controller. The forced
continuous current mode is active when the applied voltage is
less than 0.6V. Burst Mode operation will be active when the
pin is allowed to float and a Stage Shedding mode will be active
if the pin is tied to the V
CC
pin. (Do not apply voltage directly to
this pin prior to the application of voltage on the V
CC
pin.)
PGOOD:
This open-drain output is pulled low when the output
voltage has been outside the PGOOD tolerance window for the
V
PGDLY
delay of approximately 100µs.
IN
+
, IN
–
:
Inputs to a precision, unity-gain differential amplifier
with internal precision resistors. This provides true remote
sensing of both the positive and negative load terminals for
precise output voltage control.
I
TH
:
Error Amplifier Output and Switching Regulator Compen-
sation Point. All three current comparator’s thresholds in-
crease with this control voltage.
PGND:
Driver Power Ground. This pin connects directly to the
sources of the bottom N-channel external MOSFETs and the
(–) terminals of C
IN
.
PHASMD:
This pin determines the phase shift between the first
controller’s rising TG signal and the rising edge of the CLKOUT
signal. Logic 0 yields 30 degrees and Logic 1 yields 60 degrees.
Note: the
PHASMD
and
PGOOD
functions are internally tied
together on the LTC3731CUH device.
PLLIN:
Synchronization Input to Phase Detector. This pin is
internally terminated to SGND with 50kΩ. The phase-locked
loop will force the rising top gate signal of controller 1 to be
synchronized with the rising edge of the PLLIN signal.
PLLFLTR:
The phase-locked loop’s lowpass filter is tied to this
pin. Alternatively, this pin can be driven with an AC or DC
voltage source to vary the frequency of the internal oscillator.
(Do not apply voltage directly to this pin prior to the application
of voltage on the V
CC
pin.)
RUN/SS:
Combination of Soft-Start, Run Control Input and
Short-Circuit Detection Timer. A capacitor to ground at this
pin sets the ramp time to full current output as well as the time
delay prior to an output voltage short-circuit shutdown. A
minimum value of 0.01µF is recommended on this pin.
SENSE1
+
, SENSE2
+
, SENSE3
+
, SENSE1
–
, SENSE2
–
, SENSE3
–
:
The Inputs to Each Differential Current Comparator. The I
TH
pin
voltage and built-in offsets between SENSE
–
and SENSE
+
pins,
in conjunction with R
SENSE
, set the current trip threshold level.
SGND:
Signal Ground. This pin must be routed separately
under the IC to the PGND pin and then to the main ground
plane. The exposed pad on the LTC3731UH package is
SGND and must be soldered to the PCB.
SW1 to SW3:
Switch Node Connections to Inductors. Voltage
swing at these pins is from a Schottky diode (external) voltage
drop below ground to V
IN
(where V
IN
is the external MOSFET
supply rail).
TG1 to TG3:
High Current Gate Drives for Top N-channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to the boost voltage source superimposed
on the switch node voltage SW.
UVADJ:
Input to the Undervoltage Shutdown Comparator.
When the applied input voltage is less than 1.2V, this compara-
tor turns off the output MOSFET driver stages and discharges
the RUN/SS capacitor.
V
CC
:
Main Supply Pin. Because this pin supplies both the
controller circuit power as well as the high power pulses
supplied to drive the external MOSFET gates in the LTC3731CUH,
this pin needs to be very carefully and closely decoupled to the
IC’s PGND pin.
VDR:
(LTC3731G Package Only) Supplies power to the bottom
gate drivers only. This pin needs to be very carefully and closely
decoupled to the IC’s PGND pin.
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