ICS87008I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87008I is a low skew, 1:8 LVCMOS/LVTTL Clock
Generator. The device has 2 banks of 4 outputs and each
bank can be independently selected for
÷1
or
÷2
frequency
operation. Each bank also has its own power supply pins so
that the banks can operate at the following different voltage
levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/
LVTTL outputs are designed to drive 50Ω series or parallel
terminated transmission lines.
The divide select inputs, DIV_SELA and DIV_SELB, control the
output frequency of each bank. The output banks can be
independently selected for
÷1
or
÷2
operation. The bank enable
inputs, CLK_ENA and CLK_ENB, support enabling and disabling
each bank of outputs individually. The CLK_ENA and CLK_ENB
circuitry has a synchronizer to prevent runt pulses when
enabling or disabling the clock outputs. The master reset
input, nMR/OE, resets the
÷1/÷2
flip flops and also controls the
active and high impedance states of all outputs. This pin has
an internal pull-up resistor and is normally used only for test
purposes or in systems which use low power modes.
The ICS87008I is characterized to operate with the core at 3.3V
or 2.5V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,
output, and part-to-part skew characteristics make the 87008I
ideal for those clock applications demanding well-defined
performance and repeatability.
F
EATURES
• Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)
• Selectable differential CLK1, nCLK1 or
LVCMOS clock input
•
CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for
÷1
or
÷2
operation
• Glitchless, asynchronous clock enable/disable
• Output skew: 105ps (maximum) @ 3.3V core/3.3V output
• Bank skew: 70ps (maximum) @ 3.3V core/3.3V output
• 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating
supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
nMR/OE
DIV_SELA
CLK1
nCLK1
CLK0
CLK_ENA
1
0
÷
1
÷
2
1
4
0
LE
P
IN
A
SSIGNMENT
CLK1
nCLK1
V
DDOA
QA0
QA1
GND
QA2
QA3
V
DDOA
DIV_SELA
CLK_ENA
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK0
CLK_SEL
V
DDOB
QB0
QB1
GND
QB2
QB3
V
DDOB
DIV_SELB
CLK_ENB
nMR/OE
QA0:QA3
D
CLK_SEL
1
4
0
LE
QB0:QB3
ICS87008I
24-Lead TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
www.idt.com
REV. B JULY 31, 2010
CLK_ENB
D
DIV_SELB
87008AGI
1
ICS87008I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 9
4, 5, 7, 8
6, 19
10
11
12
13
14
15
16, 22
17, 18, 20, 21
23
24
Name
CLK1
nCLK1
V
DDOA
QA0, QA1,
QA2, QA3
GND
DIV_SELA
CLK_ENA
V
DD
nMR/OE
CLK_ENB
DIV_SELB
V
DDOB
QB3, QB2,
QB1, QB0
CLK_SEL
CLK0
Input
Input
Power
Output
Power
Input
Input
Power
Input
Input
Input
Power
Output
Input
Input
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup
Type
Description
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. V
DD
/2 default when left floating.
Pulldown
Output Bank A supply pins.
Bank A outputs. LVCMOS / LVTTL interface levels.
Supply ground.
Controls frequency division for Bank A outputs.
LVCMOS / LVTTL interface levels.
Output enable for Bank A outputs. Active HIGH.
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Power supply pin.
Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the
outputs to high impedance. LVCMOS / LVTTL interface levels.
Output enable for Bank B outputs. Active HIGH.
If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS / LVTTL interface levels..
Output Bank B supply pins.
Bank B outputs. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
V
DD
, V
DDOx
= 3.465V; NOTE 1
C
PD
Power Dissipation
Capacitance (per output)
V
DD
, V
DDOx
= 2.625V; NOTE 1
V
DD
= 3.465, V
DDOx
= 2.625V; NOTE 1
V
DD
= 3.465, V
DDOx
= 1.89V; NOTE 1
V
DD
= 2.625, V
DDOx
= 1.89V; NOTE 1
R
OUT
Output Impedance
7
NOTE 1: V
DDOx
denotes V
DDOA
and V
DDOB
.
Test Conditions
Minimum Typical
4
51
51
18
20
20
30
20
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
pF
pF
Ω
T
ABLE
3. F
UNCTION
T
ABLE
nMR/OE
0
1
1
1
87008AGI
Inputs
CLK_ENx
X
1
1
0
DIV_SELx
X
0
1
X
Outputs
Bank X
Qx Frequency
Hi Z
N/A
Active
Active
Low
fIN/2
fIN
N/A
www.idt.com
2
REV. B JULY 31, 2010
ICS87008I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDOA,
V
DDOB
I
DD
I
DDOA,
I
DDOB
Parameter
Power Supply Voltage
Test Conditions
Minimum
3.135
2.375
3.135
Output Supply Voltage; NOTE 1
Power Supply Current
Output Supply Current; NOTE 2
2.375
1.71
Typical
3.3
2.5
3.3
2.5
1.8
Maximum
3.465
2.625
3.465
2.625
1.89
54
6.5
Units
V
V
V
V
V
mA
mA
87008AGI
www.idt.com
REV. B JULY 31, 2010
3
ICS87008I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
Input
High Voltage
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE, CLK_SEL
CLK0
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE, CLK_SEL
CLK0
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE
CLK0, CLK_SEL
DIV_SELA, DIV_SELB,
CLK_ENA, CLK_ENB,
nMR/OE
CLK0, CLK_SEL
Test Conditions
Minimum Typical
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
V
DDOx
= 3.3V ± 5%; NOTE 2
V
OH
Output High Voltage; NOTE 1
V
DDOx
= 2.5V ± 5%; NOTE 2
V
DDOx
= 1.8V ± 5%; NOTE 2
V
DDOx
= 3.3V ± 5%; NOTE 2
V
OL
I
OZL
Output Low Voltage; NOTE 1
Output Tristate Current Low
V
DDOx
= 2.5V ± 5%; NOTE 2
V
DDOx
= 1.8V ± 5%; NOTE 2
-5
-150
-5
2.6
1.8
1.5
0.5
0.5
0.4
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
µA
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Input
Low Current
Output Tristate Current High
5
µA
I
OZH
NOTE 1: Outputs terminated with 50
Ω
to V
DDOX
/2. See Parameter Measurement Information, Output Load Test Circuits.
NOTE 2: V
DDOx
denotes V
DDOA
, and V
DDOB
.
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DD
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
nCLK1
I
IH
Input High Current
CLK1
nCLK1
I
IL
Input Low Current
CLK1
V
PP
Test Conditions
V
IN
= V
DD
= 3.465V,
V
IN
= V
DD
= 2.625V
V
IN
= V
DD
= 3.465V,
V
IN
= V
DD
= 2.625V
V
IN
= 0V, V
DD
= 3.465V,
V
IN
= 0V, V
DD
= 2.625V
V
IN
= 0V, V
DD
= 3.465V,
V
IN
= 0V, V
DD
= 2.625V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications
,
the maximum input voltage for CLK1, nCLK1 is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
87008AGI
www.idt.com
4
REV. B JULY 31, 2010
ICS87008I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
X
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay,
Low to High
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Bank Skew; NOTE 2, 6
Output Skew; NOTE 3, 6
Par t-to-Par t Skew; NOTE 4, 6
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Test Conditions
Minimum
1.9
3.0
Typical
3.5
3.7
Maximum
250
5.1
4.5
70
105
650
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
t
sk(b)
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
t
EN
20% to 80%
f
≤
133MHz
300
45
1100
55
10
t
DIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
X
Symbol Parameter
f
MAX
tp
LH
Output Frequency
Propagation Delay,
Low to High
CLK0; NOTE 1A
CLK1, nCLK1;
NOTE 1B
Bank Skew; NOTE 2, 6
Output Skew; NOTE 3, 6
Par t-to-Par t Skew; NOTE 4, 6
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Test Conditions
Minimum
2.0
3
Typical
3.8
4
Maximum
250
5.5
5
35
130
1
Units
MHz
ns
ns
ps
ps
ns
ps
%
ns
ns
t
sk(b)
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
t
EN
20% to 80%
f
≤
125MHz
300
45
1000
55
10
t
DIS
Output Disable Time; NOTE 5
10
All parameters measured at 250MHz using CLK1, nCLK1 unless noted otherwise.
NOTE 1A: Measured from the V
DD
/2 of the input to V
DDOX
/2 of the output.
NOTE 1B: Measured from the differential input crossing point to V
DDOX
/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOX
/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with
equal load conditions. Using the same type of input on each device, the output is measured at V
DDOX
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87008AGI
www.idt.com
REV. B JULY 31, 2010
5
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