Differential-to-HSTL Zero Delay Clock
Generator
ICS8725B-01
DATA SHEET
General Description
The ICS8725B-01 is a highly versatile 1:5 Differential-
to-HSTL clock generator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS8725B-01 has a fully
integrated PLL and can be configured as zero delay
buffer, multiplier or divider, and has an output frequency range of
31.25MHz to 700MHz. The reference divider, feedback divider and
output divider are each programmable, thereby allowing for the
following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve “zero delay”
between the input clock and the output clocks. The PLL_SEL pin can
be used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL and into
the internal output dividers.
Features
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Five differential HSTL output pairs
Selectable differential CLKx/nCLKx input pairs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Static phase offset: 15ps ± 135ps
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 45ps (maximum)
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
PLL_SEL
Q0
nQ0
Q1
nQ1
0
1
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
8:1, 4:1, 2:1, 1:1
1:2, 1:4, 1:8
1
Q3
nQ3
Q2
nQ2
Pin Assignment
PLL_SEL
SEL3
GND
V
DDA
V
DDO
Q4
nQ4
V
DD
CLK0
nCLK0
÷1, ÷2, ÷4, ÷8
÷16, ÷32, ÷64
0
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9
V
DD
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nFB_IN
FB_IN
SEL2
V
DDO
GND
nQ0
Q0
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
PLL
Q4
nQ4
SEL0
SEL1
SEL2
SEL3
MR
ICS8725B-01
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8725BY-01 REVISION A JULY 16, 2009
1
©2009 Integrated Device Technology, Inc.
ICS8725B-01 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1, 2,
12, 29
3
4
5
6
7
Name
SEL0, SEL1,
SEL2, SEL3
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Description
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0,
nCLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
Core supply pins.
Pullup
Pulldown
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Power supply ground.
Differential output pair. HSTL interface levels.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
8
MR
Input
Pulldown
9, 32
10
11
13, 28
14, 15
16, 17, 24,
25
18, 19
20, 21
22, 23
26, 27
30
31
V
DD
nFB_IN
FB_IN
GND
nQ0, Q0
V
DDO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
V
DDA
PLL_SEL
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS8725BY-01 REVISION A JULY 16, 2009
2
©2009 Integrated Device Technology, Inc.
ICS8725B-01 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
Q[0:4], nQ[0:4]
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
ICS8725BY-01 REVISION A JULY 16, 2009
3
©2009 Integrated Device Technology, Inc.
ICS8725B-01 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q[0:4], nQ[0:4]
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ICS8725BY-01 REVISION A JULY 16, 2009
4
©2009 Integrated Device Technology, Inc.
ICS8725B-01 Data Sheet
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
0
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
3.3
1.8
Maximum
3.465
3.465
2.0
135
16
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK_SEL,
SEL[0:3], MR
PLL_SEL
CLK_SEL,
SEL[0:3], MR
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Input High Current
I
IL
Input Low Current
ICS8725BY-01 REVISION A JULY 16, 2009
5
©2009 Integrated Device Technology, Inc.
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