Low Skew, 1-to-18
LVPECL-TO-LVCMOS / LVTTL Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 83940D is a low skew, 1-to-18 LVPECL-to-LVC-
MOS/LVTTL Fanout Buffer. The 83940D has two select-
able clock inputs. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The LVCMOS_
CLK can accept LVCMOS or LVTTL input levels. The low
impedance LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines.
The 83940D is characterized at full 3.3V and 2.5V or
mixed3.3V core, 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics make
the 83940D ideal for those clock distribution applications
demanding well defined performance and repeatability.
83940D
DATASHEET
F
EATURES
•
18 LVCMOS/LVTTL outputs
•
Selectable LVCMOS_CLK or LVPECL clock inputs
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 250MHz
•
Output skew: 150ps (maximum)
•
Part to part skew: 750ps (maximum)
•
Additive phase jitter, RMS: < 0.03ps (typical)
•
Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output
supply modes
•
0°C to 70°C ambient operating temperature
•
Lead-Free package available
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
GND
Q0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q17
Q16
Q15
GND
Q14
Q13
Q12
V
DDO
Q1
Q2
Q3
Q4
Q5
32 31 30 29 28 27 26 25
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
24
23
22
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
ICS83940D
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
83940D REVISION B 3/25/15
1
©2015 Integrated Device Technology, Inc.
83940D DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 12, 17, 25
3
4
5
6
7, 21
8, 16, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Name
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Power
Input
Input
Input
Input
Power
Power
Output
Type
Description
Power supply ground.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Pulldown input when HIGH. Selects PCLK, nPCLK inputs when
LOW. LVCMOS / LVTTL interface levels.
Pulldown Non-inverting differential LVPECL clock input.
Pullup/ Inverting differential LVPECL clock input.
Pulldown V
DD
/2 default when left floating.
Core supply pins.
Output supply pins.
Clock outputs. LVCMOS / LVTTL interface levels.
NOTE:
Pullup and Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLup
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
18
Test Conditions
Minimum
Typical
4
6
51
51
28
Maximum
Units
pF
pF
KΩ
KΩ
Ω
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
—
—
—
—
—
—
0
1
PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
—
nPCLK
1
0
Biased;
NOTE 1
Biased;
NOTE 1
0
1
—
—
Outputs
Q0:Q17
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
Non Inverting
Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
2
REVISION B 3/25/15
83940D DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Input Current, I
IN
Storage Temperature, T
STG
3.6V
-0.3V to V
DD
+ 0.3V
-0.3V to V
DDO
+ 0.3V
±20mA
-40°C to 125°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
REVISION B 3/25/15
3
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
83940D DATA SHEET
T
ABLE
4A. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°
TO
70°
Symbol
V
IH
V
IL
V
PP
V
CMR
I
IN
V
OH
V
OL
I
DD
Parameter
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
Input Current
Output High Voltage
Output Low Voltage
Core Supply Current
I
OH
= -20mA
I
OL
= 20mA
2.4
0.5
25
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
PCLK, nPCLK
500
V
DD
- 1.4
Test Conditions
Minimum
2.4
Typical
Maximum
V
DD
0.8
1000
V
DD
- 0.6
±200
Units
V
V
mV
V
µA
V
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°
TO
70°
Symbol
f
MAX
t
pLH
Parameter
Output Frequency
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
f
≤
150MHz
f
≤
150MHz
f > 150MHz
f > 150MHz
Measured on
rising edge @V
DDO
/2
f
≤
150MHz
f
≤
150MHz
f > 150MHz
f > 150MHz
Measured on
rising edge @V
DDO
/2
0.03
0.5 to 2.4V
f < 134MHz
0.3
45
50
1.1
55
1.6
1.8
1.6
1.8
Test Conditions
Minimum
Typical
Maximum
250
3.0
3.0
3.3
3.2
150
150
1.4
1.2
1.7
1.4
850
750
Units
MHz
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ps
ps
ps
ns
%
t
pLH
Propagation Delay
tsk(o)
tsk(pp)
tsk(pp)
tsk(pp)
Output Skew;
NOTE 3, 5
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
tjit
t
R
/ t
F
odc
LVCMOS_CLK
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
Output Rise/Fall Time
Output Duty Cycle
40
50
60
%
134MHz
≤
f
≤
250MHz
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 7: Driving only one input clock.
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
4
REVISION B 3/25/15
83940D DATA SHEET
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°
TO
70°
Symbol
V
IH
V
IL
V
PP
V
CMR
I
IN
V
OH
V
OL
I
DD
Parameter
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
Input Current
Output High Voltage
Output Low Voltage
Core Supply Current
I
OH
= -20mA
I
OL
= 20mA
1.8
0.5
25
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
PCLK, nPCLK
300
V
DD
- 1.4
Test Conditions
Minimum
2.4
Typical
Maximum
V
DD
0.8
1000
V
DD
- 0.6
±200
Units
V
V
mV
V
µA
V
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°
TO
70°
Symbol
f
MAX
t
pLH
Parameter
Output Frequency
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
f
≤
150MHz
f
≤
150MHz
f > 150MHz
f > 150MHz
Measured on
rising edge @V
DDO
/2
f
≤
150MHz
f
≤
150MHz
f > 150MHz
f > 150MHz
Measured on
rising edge @V
DDO
/2
0.03
0.5 to 1.8V
0.3
1.2
1.7
1.7
1.6
1.8
Test Conditions
Minimum
Typical
Maximum
250
3.2
3.0
3.4
3.3
150
150
1.5
1.3
1.8
1.5
850
750
Units
MHz
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ps
ps
ps
ns
t
pLH
Propagation Delay
tsk(o)
tsk(pp)
tsk(pp)
tsk(pp)
Output Skew;
NOTE 3, 5
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
tjit
t
R
/ t
F
LVCMOS_CLK
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
Output Rise/Fall Time
odc
Output Duty Cycle
f < 134MHz
45
50
55
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V
DDO
/2.
NOTE 2: Measured from V
DD
/2 to V
DDO
/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 7: Driving only one input clock.
REVISION B 3/25/15
5
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
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