Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
Not Recommend for New Designs
8705I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The 8705I is a highly versatile 1:8 Differential-to-LVCMOS/
LVTTL Clock Generator. The 8705I has two selectable clock
inputs. The CLK1, nCLK1 pair can accept most standard
differential input levels. The single ended CLK0 input accepts
LVCMOS or LVTTL input levels.The 8705I has a fully integrated
PLL and can be configured as zero delay buffer, multiplier
or divider and has an input and output frequency range of
15.625MHz to 250MHz. The reference divider, feedback divider
and output divider are each programmable, thereby allowing for
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test and
debug purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
F
EATURES
• Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
• Not Recommended for New Designs
For new designs, contact IDT.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
8705I REVISION E 7/13/15
1
©2015 Integrated Device Technology, Inc.
8705I DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4
5
6
7
8
9, 32
10
11
12, 16, 20, 24,
28
13, 15, 17, 19,
21, 23, 25, 27
14, 18, 22, 26
29
30
31
Name
SEL0, SEL1
CLK0
nc
CLK1
nCLK1
CLK_SEL
MR
V
DD
FB_IN
SEL2
V
DDO
Q0, Q1, Q2,
Q3, Q4, Q5,
Q6, Q7
GND
SEL3
V
DDA
PLL_SEL
Input
Input
Input
Input
Power
Input
Input
Power
Output
Power
Input
Power
Input
Pullup
Pulldown
Pullup
Pulldown
Input
Input
Type
Pulldown
Description
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
No connect.
Pulldown Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects differential CLK1, nCLK1. When
LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Pulldown reset causing the outputs to go low. When logic LOW, the internal divid-
ers and the outputs are enabled. LVCMOS/LVTTL interface levels
Core supply pins.
LVCMOS/LVTTL feedback input to phase detector for regenerating
Pulldown clocks with “zero delay”. Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
Determines output divider values in Table 3.
Pulldown
LVCMOS/LVTTL interface levels.
Output supply pins.
Clock output. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Power supply ground.
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
V
DD
, V
DDA
, V
DDO
= 3.465V
5
23
7
12
Maximum
Units
pF
KΩ
KΩ
pF
Ω
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
2
REVISION E 7/13/15
8705I DATA SHEET
T
ABLE
3A. PLL E
NABLE
F
UNCTION
T
ABLE
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)
125 - 250
62.5 - 125
31.25 - 62.5
15.625 -31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
Q0:Q7
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
3
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q0:Q7
÷8
÷8
÷8
÷ 16
÷ 16
÷ 16
÷ 32
÷ 32
÷ 64
÷ 128
÷4
÷4
÷8
÷2
÷4
÷2
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
REVISION E 7/13/15
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
8705I DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
90
15
20
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
Parameter
Input
High Voltage
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK0
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SEL3,
FB_IN, MR
CLK0
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
Input
Low Current
CLK0, CLK_SEL
MR, FB_IN,
SEL0, SEL1, SEL2, SEL3
PLL_SEL
V
OH
Output High Voltage; NOTE 1
Test Conditions
Minimum
2
2
-0.3
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
2.6
0.5
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
IH
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2. In the Parameter Measurement Information section,
see “3.3V Output Load Test Circuit” figure.
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
4
REVISION E 7/13/15
8705I DATA SHEET
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK1
nCLK1
CLK1
nCLK1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
GND + 0.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is V
DD
+ 0.3V.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
f
MAX
tp
LH
Parameter
Output Frequency
Propagation Delay,
Low-to-High; NOTE 1
CLK0
CLK1, nCLK1
CLK0
t(Ø)
Static Phase Offset;
NOTE 2, 4
PLL_SEL = 0V,
f
≤
250MHz, Qx ÷ 2
PLL_SEL = 0V,
f
≤
250MHz, Qx ÷ 2
PLL_SEL = 3.3V,
fREF
≤
200MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF
≤
167MHz, Qx ÷ 1
PLL_SEL = 3.3V,
fREF = 200MHz, Qx ÷ 1
PLL_SEL = 0V
PLL_SEL = 0V
f
OUT
> 40MHz
400
400
Test Conditions
Minimum
15.625
5
5
-100
-15
-50
25
+135
+100
Typical
Maximum
250
7
7.3
150
285
250
65
55
45
1
950
950
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
mS
ps
ps
%
CLK1, nCLK1
CLK0
tsk(o)
tjit(cc)
t
L
t
R
t
F
Output Skew;
NOTE 3, 4
CLK1, nCLK1
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
Output Rise Time
Output Fall Time
odc
Output Duty Cycle
43
57
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
REVISION E 7/13/15
5
Zero Delay, Differential-to-LVCMOS/
LVTTL Clock Generator
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