Low Skew, 1-To-2, Differential-To-CML
Fanout Buffer
ICS858S011I
Datasheet
Description
The ICS858S011I is a high-speed 1-to-2 Differential-to-CML Fanout
Buffer. The device is optimized for high-speed and very low output
skew, making it suitable for use in demanding applications such as
SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and V
REF
_
AC
pin allow other
differential signal families such as LVDS, LVPECL, SSTL, and CML
to be easily interfaced to the input with minimal use of external
components.
The ICS858S011I is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
•
•
•
•
•
•
•
•
•
•
Two differential CML outputs
IN/nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Output skew: 25ps (maximum)
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.042ps (typical)
Propagation delay: 525ps (maximum)
Operating voltage supply range:
V
CC
= 2.375V to 3.63V, V
EE
= 0V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
IN
V
T
nIN
R
IN
R
IN
Q1
V
REF_AC
nQ1
nQ0
Pin Assignment
V
CC
V
EE
V
EE
V
cc
IN 1
V
T
2
16 15 14 13
12 Q0
11 nQ0
10 nQ1
9 Q1
5
V
CC
V
REF_AC
3
nIN 4
6
V
EE
7
V
EE
8
V
CC
ICS858S011I
16-Lead VFQFN
3mm x 3mm x 0.925
mm package body
K Package
Top View
© Integrated Device Technology, Inc.
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September 19, 2017
ICS858S011I Datasheet
Table 1. Pin Descriptions
Number
1
2
3
4
5, 8, 13, 16
6, 7, 14, 15
9, 10
11, 12
Name
IN
V
T
V
REF_AC
nIN
V
CC
V
EE
Q1, nQ1
nQ0, Q0
Type
Input
Input
Output
Input
Power
Power
Output
Output
Description
Non-inverting differential LVPECL clock input.
Termination input.
Reference voltage for AC-coupled applications.
Inverting differential LVPECL clock input.
Power supply pins.
Negative supply pins.
Differential output pair. CML interface levels.
Differential output pair. CML interface levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN/nIN
V
T
Current, I
VT
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
JA
(Junction-to-Ambient)
Rating
4.6V (CML mode, V
EE
= 0V)
-0.5V to V
CC
+ 0.5V
20mA
40mA
+50mA
+100mA
±2mA
-40°C to 85°C
-65C to 150C
74.7C/W (0 mps)
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.63
57
Units
V
mA
© Integrated Device Technology, Inc.
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ICS858S011I Datasheet
Table 2B. DC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
IN to V
T
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Voltage between IN and V
T
Reference Voltage
IN/nIN
V
CC
– 1.4
V
CC
– 1.3
IN/nIN
IN/nIN
IN/nIN
Test Conditions
IN to V
T
, nIN to V
T
Minimum
40
1.2
0
0.15
0.3
1.28
V
CC
– 1.2
Typical
50
Maximum
60
V
CC
V
IH
– 0.15
1.2
Units
V
V
V
V
V
V
NOTE 1: Refer to Parameter Measurement Information,
Input Voltage Swing Diagram.
Table 2C. CML DC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OUT
Parameter
Output High Voltage; NOTE 1
Output Voltage Swing
Test Conditions
Minimum
V
CC
– 0.020
325
650
40
Typical
V
CC
– 0.010
400
800
50
60
Maximum
V
CC
Units
V
mV
mV
V
DIFF_OUT
Differential Output Voltage Swing
R
OUT
Output Source Impedance
NOTE 1: Outputs terminated with 50
to V
CC
.
AC Electrical Characteristics
Table 3. AC Characteristics,
V
CC
= 2.375V to 3.63V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay, Differential;
NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
155.52MHz @ 3.3V, Integration
Range: 12kHz – 20MHz
20% to 80%
60
0.042
200
275
Test Conditions
Minimum
Typical
Maximum
2
525
25
250
Units
GHz
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters characterized at
1.2GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage, same temperature, same frequency and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
© Integrated Device Technology, Inc.
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September 19, 2017
ICS858S011I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.042ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “Rohde & Schwarz SMA100A Low Noise
Signal Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”.
© Integrated Device Technology, Inc.
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September 19, 2017
ICS858S011I Datasheet
Parameter Measurement Information
0V
Qx
SCOPE
V
CC
CML Driver
V
EE
V
CC
Power
Supply
nIN
V
IN
Cross Points
V
IH
IN
V
IL
-2.375V to -3.63V
V
EE
CML Output Load AC Test Circuit
Differential Input Level
Par t 1
nQx
nQx
Qx
Qx
nQy
Qy
tsk(pp)
Par t 2
nQy
Qy
Part-to-Part Skew
Output Skew
nIN
IN
V
IN
, V
OUT
400mV
(typical)
V
DIFF_IN
, V
DIFF_OUT
800mV
(typical)
nQ0, nQ1
Q0, Q1
t
PD
Single-ended & Differential Input Voltage Swing
Propagation Delay
© Integrated Device Technology, Inc.
5
September 19, 2017
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