AS4C64M32MD2-25BCN
AS4C128M16MD2-25BCN
KEY FEATURE
•Double-data
rate architecture; two data transfers per clock cycle
• Bidirectional data strobes (DQS, DQS#), These are transmitted/received with data to be used in capturing data at the
receiver
• Differential clock inputs (CK and CK#)
• Differential data strobes (DQS and DQS#)
• Commands & addresses entered on both positive and negative CK edges; data and data mask referenced to both
edges of DQS
• 8 internal banks for concurrent operation
• Data mask (DM) for write data
• Burst Length: 4 (default), 8 or 16
• Burst Type: Sequential or Interleave
• Read & Write latency : Refer to Table 51 LPDDR2 AC Timing Table
• Auto Precharge option for each burst access
• Configurable Drive Strength
• Auto Refresh and Self Refresh Modes
• Partial Array Self Refresh and Temperature Compensated Self Refresh
• Deep Power Down Mode
• HSUL_12 compatible inputs
• VDD1/VDD2/VDDQ/VDDCA
: 1.8V/1.2V/1.2V/1.2V
• No DLL : CK to DQS is not synchronized
• Edge aligned data output, center aligned data input
• Operating Temperature : -30 to 85 °C
• Auto refresh duty cycle : 3.9us
• Package type : 134-ball FBGA 10x11.5x1.0mm (max)
Table 1. Ordering Information
Part Number
Org
Temperature
MaxClock (MHz)
400
400
Package
134-ball FBGA
134-ball FBGA
AS4C128M16MD2-25BCN
128Mx16
Commercial
-30°C to +85°C
AS4C64M32MD2-25BCN
64Mx32
Table 2. Speed Grade Information
Speed Grade
DDR2L-800
Clock Frequency
400MHz
RL
6
WL
3
Commercial
-30°C to +85°C
tRCD (ns)
18
tRP (ns)
18
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AS4C64M32MD2-25BCN
AS4C128M16MD2-25BCN
2. Ball Descriptions and PKG Dimension/Ballout
2.1 Pin Definition and Description
Name
Type
Input
Description
CK, CK#
CKE
Input
CS#
CA0 - CA9
DQ0 - DQ15
(x16)
DQ0 - DQ31
(x32)
DQS0,
DQS0#,
DQS1,
DQS1#
(x16)
DQS0 -
DQS3,
DQS0# -
DQS3#
(x32)
DM0-DM1
(x16)
DM0 - DM3
(x32)
Input
Clock:
CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA inputs are
sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS#
and CKE, are sampled at the positive Clock edge.
Clock is defined as the differential pair, CK and CK#. The positive Clock edge is defined by
the crosspoint of a rising CK and a falling CK#. The negative Clock edge is defined by the
crosspoint of a falling CK and a rising CK#.
Clock Enable:
CKE HIGH activates and CKE LOW deactivates internal clock signals and
therefore device input buffers and output drivers. Power savings modes are entered and
exited through CKE transitions.
CKE is considered part of the command code. See
Command Truth Table
for command
code descriptions.
CKE is sampled at the positive Clock edge.
Chip Select:
CS# is considered part of the command code. See
Command Truth Table
for command code descriptions.
CS# is sampled at the positive Clock edge.
Input
DDR Command/Address Inputs:
Uni-directional command/address bus inputs.
CA is considered part of the command code. See
Command Truth Table
for command code
descriptions.
Data Inputs/Output: Bi-directional data bus
I/O
I/O
Data Strobe (Bi-directional, Differential):
The data strobe is bi-directional (used for read
and write data) and differential (DQS and DQS#). It is output with read data and input with
write data. DQS is edge-aligned to read data and centered with write data.
For x16, DQS0 and DQS0# correspond to the data on DQ0 - DQ7; DQS1 and DQS1# to
the data on DQ8 - DQ15.
For x32 DQS0 and DQS0# correspond to the data on DQ0 - DQ7, DQS1 and
DQS1# to the data on DQ8 - DQ15, DQS2 and DQS2# to the data on DQ16 - DQ23, DQS3
and DQS3# to the data on DQ24 - DQ31.
Input
VDD1
VDD2
VDDCA
VDDQ
VREF(CA)
VREF(DQ)
VSS
VSSCA
VSSQ
ZQ
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
I/O
NOTE : Data includes DQ and DM
Input Data Mask:
For LPDDR2 devices that do not support the DNV feature, DM is the
input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of
DQS. Although DM is for input only, the DM loading shall match the DQ and DQS (or
DQS#).
DM0 is the input data mask signal for the data on DQ0-7.
For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15.
For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is
the input data mask signal for the data on DQ24-31.
Core Power Supply 1:
Core power supply
Core Power Supply 2:
Core power supply
Input Receiver Power Supply:
Power supply for CA0-9, CKE, CS#, CK, and CK# input
buffers.
I/O Power Supply:
Power supply for Data input/output buffers.
Reference Voltage for CA Command and Control Input Receiver:
Reference voltage for
all CA0-9, CKE, CS#, CK, and CK# input buffers.
Reference Voltage for DQ Input Receiver:
Reference voltage for all Data input buffers
Ground
Ground for Input Receivers
I/O Ground
Reference Pin for Output Drive Strength Calibration
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