2:1 Multiplexer and 1:2 Demultiplexer with
Pre-Emphasis
ICS854S713I
DATA SHEET
General Description
The ICS854S713I is a differential, high-speed 2:1 data/clock
multiplexer and 1:2 clock/data demultiplexer in one device. The
outputs support pre-emphasis in order to drive backplanes and long
transmission lines while reducing inter-symbol interference effects.
The pre-emphasis level is individually configurable to optimize for low
bit error rate or power consumption. Pre-emphasis utilizes an
increased output voltage swing for transition bits. The device is
optimized for data rates up to 4.5Gbps (NRZ) and for deterministic
jitter in data applications and low additive jitter in clock applications.
The outputs are LVDS-compliant while the differential input is
compatible with a variety of signal levels such as LVDS, LVPECL and
CML. A small package (4.0mm x 4.0mm 24-lead VFQFN) supports
space-efficient board designs. The ICS854S713I operates from a
3.3V power supply and supports the industrial temperature range of
-40 to +85 deg C.
Features
•
•
•
•
•
•
•
•
•
•
•
•
2:1 differential data/clock multiplexer and 1:2 data/clock
demultiplexer with a two-output fanout
4.5 Gbps max. data rate (NRZ)
Differential LVDS outputs
Differential inputs supporting LVDS, LVPECL and CML levels
Configurable output pre-emphasis
Low-skew output: 25ps (maximum)
Low data deterministic jitter: 3ps (maximum)
LVCMOS interface levels for the control inputs
Additive phase jitter, RMS: 0.09ps (typical)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
nCLKA0
CLKA0
PEA
DNU
SLEA
GND
Block Diagram
PEA
CLKA0
Pulldown
Pulldown
Pulldn/up
Pulldown
Pulldn/up
Pulldown
Pulldown
Pulldown
24 23 22 21 20 19
CLKA1
nCLKA1
QB0
nQB0
QB1
nQB1
1
2
3
4
5
6
7 8
9 10 11 12
18
17
16
15
14
13
QA
nQA
VDD
GND
CLKB
nCLKB
0
QA
nQA
1
nCLKA0
CLKA1
nCLKA1
SELA
VDD
GND
PEB0
PEB1
SELB
VDD
PEB0
PEB1
CLKB
nCLKB
QB0
Pulldown
Pulldn/up
ICS854S713I
24 lead VFQFN
4.0mm x 4.0mm x 0.925mm
package body
K Package
Top View
0
nQB0
QB1
1
nQB1
SELB
Pulldown
ICS854S713AKI REVISION A OCTOBER 5, 2010
1
©2010 Integrated Device Technology, Inc.
ICS854S713I Data Sheet
2:1 MULTIPLEXER and 1:2 DEMULTIPLEXER WITH PRE-EMPHASIS
Table 1. Pin Descriptions
Number
1
2
3, 4
5, 6
7, 12, 16
8, 15, 19
9,
10
11
13
14
17, 18
20
21
22
23
24
Name
CLKA1
nCLKA1
QB0, nQB0
QB1, nQB1
V
DD
GND
PEB0, PEB1
SELB
nCLKB
CLKB
nQA, QA
SELA
DNU
PEA
CLKA0
nCLKA0
Input
Input
Output
Output
Power
Power
Input
Input
Input
Input
Output
Input
Reserved
Input
Input
Input
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential data and clock input.
LVDS, LVPECL or CML interface levels.
Inverting differential data and clock input. LVDS, LVPECL or CML interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply pins.
Power supply ground.
Pre-emphasis control inputs for the QB0 and QB1 outputs.
LVCMOS/LVTTL interface levels. See table 3D for function.
Demultiplexer select control input. LVCMOS/LVTTL interface levels.
See Table 3B for function.
Inverting differential data and clock input. LVDS, LVPECL or CML interface levels.
Non-inverting differential data and clock input.
LVDS, LVPECL or CML interface levels.
Differential output pair. LVDS interface levels.
Multiplexer select control input. LVCMOS/LVTTL interface levels.
See Table 3A for function.
Do not use (reserved).
Pre-emphasis control input for the QA output. LVCMOS/LVTTL interface levels.
See Table 3C for function.
Non-inverting differential data and clock input.
LVDS, LVPECL or CML interface levels.
Inverting differential data and clock input. LVDS, LVPECL or CML interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
Ω
k
Ω
ICS854S713AKI REVISION A OCTOBER 5, 2010
2
©2010 Integrated Device Technology, Inc.
ICS854S713I Data Sheet
2:1 MULTIPLEXER and 1:2 DEMULTIPLEXER WITH PRE-EMPHASIS
Device Configuration
Table 3A. Multiplexer Select Control
Input
SELA
0 (default)
1
QA
CLKA0
CLKA1
1
QB0 = LOW
nQB0 = HIGH
Table 3B. Demultiplexer Select Control
Input
SELB
0 (default)
QB0
CLKB
Outputs
QB1
QB1 = LOW
nQB1 = HIGH
CLKB
NOTE: SELA is an asynchronous control.
NOTE: SELB is an asynchronous control.
Table 3C. Output Pre-Emphasis Control for QA
Input
PEA
0 (default)
1
Pre-Emphasis
QA
Off
On
PEB1
0 (default)
0
1
1
Table 3D. Output Pre-Emphasis Control for QB0, QB1
Input
PEB0
0 (default)
1
0
1
QB1
Off
Off
On
On
Pre-Emphasis
QB0
Off
On
Off
On
NOTE: PEA is an asynchronous control.
NOTE: PEBx are asynchronous controls.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
58.9°C (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
115
Units
V
mA
ICS854S713AKI REVISION A OCTOBER 5, 2010
3
©2010 Integrated Device Technology, Inc.
ICS854S713I Data Sheet
2:1 MULTIPLEXER and 1:2 DEMULTIPLEXER WITH PRE-EMPHASIS
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
PEA
PEB0, PEB1,
SELA, SELB
PEA
PEB0, PEB1,
SELA, SELB
V
DD
= V
IN
= 3.465V
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
I
IL
Input Low Current
V
DD
= 3.465V, V
IN
= 0V
-10
µA
Table 4C. DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
V
IN
V
DIFF_IN
Parameter
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Test Conditions
Minimum
1.2
0
0.15
0.3
Typical
Maximum
V
DD
V
IH
- 0.15
1.2
2.4
Units
V
V
V
V
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram.
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.15
1.25
Test Conditions
Pre-Emphasis off (PEx0 = PEx1= 0)
Minimum
350
Typical
450
Maximum
600
50
1.35
50
Units
mV
mV
V
mV
ICS854S713AKI REVISION A OCTOBER 5, 2010
4
©2010 Integrated Device Technology, Inc.
ICS854S713I Data Sheet
2:1 MULTIPLEXER and 1:2 DEMULTIPLEXER WITH PRE-EMPHASIS
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to +85°C
Symbol
f
REF
f
OUT
Parameter
Input Reference Frequency
Output Frequency
Operating Data Rate
Test Conditions
Alternating 01 pattern (Clock)
Alternating 01 pattern (Clock)
NRZ (PRBS 2
7
-1 Pattern)
CLKA0 or CLKA1 to QA
Alternating 01 pattern (Clock)
CLKB to QB0 or QB1
Alternating 01 pattern (Clock)
Alternating 01 pattern (Clock)
Alternating 01 pattern (Clock)
Alternating 01 pattern (Clock)
f
OUT
= 300MHz, PEx = 0
f
OUT
= 300MHz, PEx = 1
f
OUT
= 300MHz, PEx = 1
Alternating 01 pattern (Clock), 491.52MHz,
Integration Range: 12kHz - 20MHz
K28.5 Pattern, 1.5Gbps,
Pre-Emphasis On
NRZ (PRBS 2
7
-1 Pattern), 1.5Gbps,
Pre-Emphasis On
80
20% to 80%, Alternating 01 pattern (Clock)
Alternating 01 pattern (Clock), QA
≤
1GHz
125
80
-45
0
2
255
0.09
200
200
Minimum
Typical
Maximum
3.0
3.0
4.5
500
500
25
25
100
Units
GHz
GHz
Gbps
ps
ps
ps
ps
ps
dB
dB
ps
ps
t
PD
Propagation Delay; NOTE 1
tsk(p)
tsk(o)
tsk(pp)
V
PE
∆t
PE
tjit
Output Pulse Skew
Output Skew, NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Pre-Emphasis Voltage
Ratio
Output Pre-Emphasis Duration
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter section
Deterministic Jitter Peak-Peak;
NOTE 5
Total Jitter Peak-Peak
Output Rise/
Fall Time
f
OUT
≤
625MHz
f
OUT
=1.25GHz
f
OUT
=2.25GHz
t
DJ
t
TJ
3
4
400
200
100
ps
ps
ps
ps
ps
dB
t
R
/ t
F
MUX_
ISOL
MUX Isolation
NOTE: All parameters characterized at f
OUT
≤
1.25GHz and pre-emphasis off, unless otherwise noted.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined according with JEDEC Standard 65.
NOTE 5: A repeating K28.5 sequence (composed of alternating K28.5+ and K28.5-) contains the symbols 0011111010 1100000101. This
pattern contains five consecutive 1's and five consecutive 0's, (the longest consecutive identical digits found in 8B/10B coded data).
ICS854S713AKI REVISION A OCTOBER 5, 2010
5
©2010 Integrated Device Technology, Inc.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
