nRF52832 Product Specification
v1.3
Key features
•
2.4 GHz transceiver
•
•
-96 dBm sensitivity in
Bluetooth
®
low energy mode
2 Mbps
Bluetooth®
low energy mode
Applications
•
Internet of Things (IoT)
•
Home automation
•
Sensor networks
•
Building automation
•
Industrial
•
Retail
Personal area networks
•
•
Health/fitness sensor and monitor devices
•
Medical devices
•
Key fobs and wrist watches
Interactive entertainment devices
•
Remote controls
•
Gaming controllers
Beacons
A4WP wireless chargers and devices
Remote control toys
Computer peripherals and I/O devices
•
•
•
•
Mouse
Keyboard
Multi-touch trackpad
Gaming
•
•
1 Mbps, 2 Mbps supported data rates
•
TX power -20 to +4 dBm in 4 dB steps
•
Single-pin antenna interface
•
5.3 mA peak current in TX (0 dBm)
•
5.4 mA peak current in RX
•
RSSI (1 dB resolution)
®
Cortex
®
-M4 32-bit processor with FPU, 64 MHz
ARM
215 EEMBC CoreMark
®
score running from flash memory
58 μA/MHz running from flash memory
51.6 μA/MHz running from RAM
Data watchpoint and trace (DWT), embedded trace macrocell (ETM), and
instrumentation trace macrocell (ITM)
•
Serial wire debug (SWD)
•
Trace port
Flexible power management
•
Supply voltage range 1.7 V–3.6 V
•
Fully automatic LDO and DC/DC regulator system
•
Fast wake-up using 64 MHz internal oscillator
•
0.3 μA at 3 V in OFF mode
•
0.7 μA at 3 V in OFF mode with
full 64
kB RAM retention
•
1.9 μA at 3 V in ON mode, no RAM retention, wake on RTC
Memory
•
512 kB flash/64 kB RAM
•
256 kB flash/32 kB RAM
Nordic SoftDevice ready
Support for concurrent multi-protocol
Type 2 near field communication (NFC-A) tag with wakeup-on-field and touch-
to-pair capabilities
12-bit, 200 ksps ADC - 8 configurable channels with programmable gain
64 level comparator
15 level low power comparator with wakeup from System OFF mode
Temperature sensor
32 general purpose I/O pins
3x 4-channel pulse width modulator (PWM) units with EasyDMA
Digital microphone interface (PDM)
5x 32-bit timers with counter mode
Up to 3x SPI master/slave with EasyDMA
Up to 2x I2C compatible 2-Wire master/slave
I2S with EasyDMA
UART (CTS/RTS) with EasyDMA
Programmable peripheral interconnect (PPI)
Quadrature decoder (QDEC)
AES HW encryption with EasyDMA
Autonomous peripheral operation without CPU intervention using PPI and
EasyDMA
3x real-time counter (RTC)
External system
•
Single crystal operation
•
On-chip balun (single-ended RF)
•
Few external components
Package variants
•
•
QFN48 package, 6 × 6 mm
WLCSP package, 3.0 × 3.2 mm
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
2017-02-03
Contents
Contents
1 Revision history................................................................................... 9
2 About this document............................................................................................ 10
2.1 Peripheral naming and abbreviations................................................................................... 10
2.2 Register tables...................................................................................................................... 10
2.3 Registers............................................................................................................................... 11
3 Block diagram........................................................................................................12
4 Pin assignments.................................................................................................... 13
4.1 QFN48 pin assignments....................................................................................................... 13
4.2 WLCSP ball assignments..................................................................................................... 15
4.3 GPIO usage restrictions........................................................................................................17
5 Absolute maximum ratings.................................................................................. 19
6 Recommended operating conditions.................................................................. 20
7 CPU......................................................................................................................... 21
7.1 Floating point interrupt.......................................................................................................... 21
7.2 Electrical specification........................................................................................................... 21
7.3 CPU and support module configuration................................................................................22
8 Memory................................................................................................................... 23
8.1
8.2
8.3
8.4
RAM - Random access memory...........................................................................................23
Flash - Non-volatile memory.................................................................................................24
Memory map......................................................................................................................... 24
Instantiation........................................................................................................................... 24
9 AHB multilayer.......................................................................................................26
9.1 AHB multilayer priorities........................................................................................................26
10 EasyDMA.............................................................................................................. 27
10.1 EasyDMA array list............................................................................................................. 28
11 NVMC — Non-volatile memory controller......................................................... 29
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Writing to Flash...................................................................................................................29
Erasing a page in Flash..................................................................................................... 29
Writing to user information configuration registers (UICR)................................................. 29
Erasing user information configuration registers (UICR).................................................... 29
Erase all.............................................................................................................................. 30
Cache.................................................................................................................................. 30
Registers............................................................................................................................. 30
Electrical specification......................................................................................................... 33
12 BPROT — Block protection................................................................................34
12.1 Registers............................................................................................................................. 34
13 FICR — Factory information configuration registers.......................................43
13.1 Registers............................................................................................................................. 43
14 UICR — User information configuration registers........................................... 54
14.1 Registers............................................................................................................................. 54
15 Peripheral interface............................................................................................. 68
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Peripheral ID....................................................................................................................... 68
Peripherals with shared ID..................................................................................................68
Peripheral registers............................................................................................................. 69
Bit set and clear..................................................................................................................69
Tasks................................................................................................................................... 69
Events..................................................................................................................................70
Shortcuts............................................................................................................................. 70
Interrupts............................................................................................................................. 70
Page 2
Contents
16 Debug and trace.................................................................................................. 72
16.1
16.2
16.3
16.4
16.5
DAP - Debug Access Port.................................................................................................. 72
CTRL-AP - Control Access Port......................................................................................... 73
Debug interface mode.........................................................................................................74
Real-time debug.................................................................................................................. 74
Trace................................................................................................................................... 75
17 Power and clock management...........................................................................76
17.1 Current consumption scenarios.......................................................................................... 76
18 POWER — Power supply....................................................................................78
18.1 Regulators........................................................................................................................... 78
18.2 System OFF mode..............................................................................................................79
18.3 System ON mode............................................................................................................... 80
18.4 Power supply supervisor.....................................................................................................80
18.5 RAM sections...................................................................................................................... 82
18.6 Reset................................................................................................................................... 82
18.7 Retained registers............................................................................................................... 83
18.8 Reset behavior.................................................................................................................... 83
18.9 Registers............................................................................................................................. 83
18.10 Electrical specification....................................................................................................... 99
19 CLOCK — Clock control...................................................................................101
19.1
19.2
19.3
19.4
20.1
20.2
20.3
20.4
21.1
21.2
21.3
21.4
21.5
HFCLK clock controller..................................................................................................... 101
LFCLK clock controller......................................................................................................103
Registers........................................................................................................................... 105
Electrical specification....................................................................................................... 109
Pin configuration............................................................................................................... 111
GPIO located near the RADIO......................................................................................... 113
Registers........................................................................................................................... 113
Electrical specification....................................................................................................... 154
Pin events and tasks........................................................................................................ 157
Port event..........................................................................................................................158
Tasks and events pin configuration.................................................................................. 158
Registers........................................................................................................................... 158
Electrical specification....................................................................................................... 167
20 GPIO — General purpose input/output........................................................... 111
21 GPIOTE — GPIO tasks and events..................................................................157
22 PPI — Programmable peripheral interconnect............................................... 168
22.1 Pre-programmed channels................................................................................................169
22.2 Registers........................................................................................................................... 169
23 RADIO — 2.4 GHz Radio.................................................................................. 205
23.1 EasyDMA...........................................................................................................................205
23.2 Packet configuration..........................................................................................................206
23.3 Maximum packet length.................................................................................................... 207
23.4 Address configuration........................................................................................................207
23.5 Data whitening.................................................................................................................. 207
23.6 CRC...................................................................................................................................208
23.7 Radio states...................................................................................................................... 209
23.8 Transmit sequence............................................................................................................209
23.9 Receive sequence.............................................................................................................211
23.10 Received Signal Strength Indicator (RSSI).....................................................................212
23.11 Interframe spacing...........................................................................................................212
23.12 Device address match.................................................................................................... 213
23.13 Bit counter....................................................................................................................... 213
23.14 Registers......................................................................................................................... 214
23.15 Electrical specification..................................................................................................... 230
24 TIMER — Timer/counter....................................................................................234
24.1 Capture..............................................................................................................................235
24.2 Compare............................................................................................................................235
Page 3
Contents
24.3
24.4
24.5
24.6
Task delays....................................................................................................................... 235
Task priority.......................................................................................................................235
Registers........................................................................................................................... 235
Electrical specification....................................................................................................... 241
25 RTC — Real-time counter.................................................................................242
25.1 Clock source..................................................................................................................... 242
25.2 Resolution versus overflow and the PRESCALER........................................................... 242
25.3 COUNTER register............................................................................................................243
25.4 Overflow features.............................................................................................................. 243
25.5 TICK event........................................................................................................................ 243
25.6 Event control feature.........................................................................................................244
25.7 Compare feature............................................................................................................... 244
25.8 TASK and EVENT jitter/delay........................................................................................... 246
25.9 Reading the COUNTER register.......................................................................................248
25.10 Registers......................................................................................................................... 248
25.11 Electrical specification..................................................................................................... 254
26 RNG — Random number generator................................................................ 255
26.1
26.2
26.3
26.4
Bias correction.................................................................................................................. 255
Speed................................................................................................................................ 255
Registers........................................................................................................................... 255
Electrical specification....................................................................................................... 257
27 TEMP — Temperature sensor.......................................................................... 258
27.1 Registers........................................................................................................................... 258
27.2 Electrical specification....................................................................................................... 263
28 ECB — AES electronic codebook mode encryption...................................... 264
28.1
28.2
28.3
28.4
28.5
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
29.9
Shared resources.............................................................................................................. 264
EasyDMA...........................................................................................................................264
ECB data structure............................................................................................................264
Registers........................................................................................................................... 265
Electrical specification....................................................................................................... 266
Shared resources.............................................................................................................. 268
Encryption..........................................................................................................................268
Decryption......................................................................................................................... 268
AES CCM and RADIO concurrent operation.................................................................... 269
Encrypting packets on-the-fly in radio transmit mode.......................................................269
Decrypting packets on-the-fly in radio receive mode........................................................270
CCM data structure...........................................................................................................271
EasyDMA and ERROR event........................................................................................... 272
Registers........................................................................................................................... 272
29 CCM — AES CCM mode encryption................................................................267
30 AAR — Accelerated address resolver.............................................................276
30.1 Shared resources.............................................................................................................. 276
30.2 EasyDMA...........................................................................................................................276
30.3 Resolving a resolvable address........................................................................................276
30.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................277
30.5 IRK data structure............................................................................................................. 277
30.6 Registers........................................................................................................................... 278
30.7 Electrical specification....................................................................................................... 280
31 SPIM — Serial peripheral interface master with EasyDMA............................281
31.1
31.2
31.3
31.4
31.5
31.6
31.7
Shared resources.............................................................................................................. 281
EasyDMA...........................................................................................................................282
SPI master transaction sequence..................................................................................... 283
Low power.........................................................................................................................284
Master mode pin configuration......................................................................................... 284
Registers........................................................................................................................... 285
Electrical specification....................................................................................................... 290
Page 4
Contents
32 SPIS — Serial peripheral interface slave with EasyDMA...............................292
32.1
32.2
32.3
32.4
32.5
32.6
33.1
33.2
33.3
33.4
33.5
33.6
33.7
33.8
33.9
Shared resources.............................................................................................................. 292
EasyDMA...........................................................................................................................292
SPI slave operation...........................................................................................................293
Pin configuration............................................................................................................... 294
Registers........................................................................................................................... 295
Electrical specification....................................................................................................... 303
2
33 TWIM — I C compatible two-wire interface master with EasyDMA...............305
Shared resources.............................................................................................................. 306
EasyDMA...........................................................................................................................306
Master write sequence......................................................................................................307
Master read sequence...................................................................................................... 308
Master repeated start sequence....................................................................................... 309
Low power.........................................................................................................................310
Master mode pin configuration......................................................................................... 310
Registers........................................................................................................................... 310
Electrical specification....................................................................................................... 317
2
34 TWIS — I C compatible two-wire interface slave with EasyDMA.................. 319
34.1 Shared resources.............................................................................................................. 321
34.2 EasyDMA...........................................................................................................................321
34.3 TWI slave responding to a read command.......................................................................321
34.4 TWI slave responding to a write command...................................................................... 322
34.5 Master repeated start sequence....................................................................................... 323
34.6 Terminating an ongoing TWI transaction..........................................................................324
34.7 Low power.........................................................................................................................324
34.8 Slave mode pin configuration........................................................................................... 324
34.9 Registers........................................................................................................................... 325
34.10 Electrical specification..................................................................................................... 331
35 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 333
35.1 Shared resources.............................................................................................................. 333
35.2 EasyDMA...........................................................................................................................333
35.3 Transmission..................................................................................................................... 334
35.4 Reception.......................................................................................................................... 334
35.5 Error conditions................................................................................................................. 336
35.6 Using the UARTE without flow control............................................................................. 336
35.7 Parity configuration............................................................................................................336
35.8 Low power.........................................................................................................................336
35.9 Pin configuration............................................................................................................... 337
35.10 Registers......................................................................................................................... 337
35.11 Electrical specification..................................................................................................... 345
36 QDEC — Quadrature decoder.......................................................................... 347
36.1
36.2
36.3
36.4
36.5
36.6
36.7
36.8
37.1
37.2
37.3
37.4
37.5
37.6
37.7
Sampling and decoding.................................................................................................... 347
LED output........................................................................................................................ 348
Debounce filters................................................................................................................ 348
Accumulators.....................................................................................................................349
Output/input pins............................................................................................................... 349
Pin configuration............................................................................................................... 349
Registers........................................................................................................................... 350
Electrical specification....................................................................................................... 356
Shared resources.............................................................................................................. 357
Overview............................................................................................................................357
Digital output..................................................................................................................... 358
Analog inputs and channels..............................................................................................359
Operation modes...............................................................................................................359
EasyDMA...........................................................................................................................361
Resistor ladder.................................................................................................................. 362
37 SAADC — Successive approximation analog-to-digital converter............... 357
Page 5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
