GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) may
be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is
implemented with GSI's high performance CMOS technology
and is available in JEDEC-standard 100-pin TQFP and
165-bump FP-BGA packages.
Functional Description
The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is an
18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like
ZBT, NtRAM, NoBL or other pipelined read/double late write
or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Parameter Synopsis
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow
Through
2-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
Curr
(x18)
Curr
(x32/x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
280
330
275
320
5.5
5.5
175
200
175
200
255
300
250
295
6.0
6.0
165
190
165
190
230
270
230
265
6.5
6.5
160
180
160
180
200
230
195
225
7.0
7.0
150
170
150
170
185
215
180
210
7.5
7.5
145
165
145
165
165
190
165
185
8.5
8.5
135
150
135
150
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
Rev: 2.15 11/2004
1/36
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A
DQ
B
DQ
C
DQ
D
TMS
TDI
TDO
TCK
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
I
I
O
I
In
In
In
In
In
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
Core power supply
Ground
Output driver power supply
Rev: 2.15 11/2004
4/36
© 1998, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
