TMC2246A
Image Filter
11 x 10 bit, 60 MHz
Features
•
•
•
•
•
•
•
60 MHz computation rate
60 MHz data and coefficient input
Four 11 x 10-bit multipliers
Individual data and coefficient inputs
25-Bit accumulator
Fractional and integer two’s complement data formats
Input and output data latches with user-configurable
enables
• Selectable 16-bit rounded output
• Internal 1/2 LSB rounding
• Available in 120-pin CPGA, PPGA, MPGA, or MQFP
Applications
•
•
•
•
•
•
Fast pixel interpolation
Fast image manipulation
Image mixing and keying
High-performance FIR filters
Adaptive digital filters
One- and two-dimensional image processing
Description
The TMC2246A is a video-speed convolutional array com-
posed of four 11 x 10 bit registered multipliers followed by a
summer and an accumulator. All eight multiplier inputs are
accessible to the user and may be updated every clock cycle
with integer or fractional two’s complement data. A pipe-
lined architecture, fully registered input and output ports,
and asynchronous three-state output enable control simplify
the design of complex systems.
The data or coefficient inputs to the multipliers may be held
over multiple clock cycles, providing storage for mixing and
filtering coefficients. The 25-bit internal accumulator path
allows two bits of cumulative word growth and may be inter-
nally rounded to 16 bits. Output data are updated every clock
cycle, or may be held under user control. All data inputs, out-
puts, and controls are TTL compatible and (except for the
three-state output enable) are registered on the rising edge of
CLK.
The TMC2246A is uniquely suited to performing pixel inter-
polation in image manipulation and filtering applications. As
a companion to the Fairchild Semiconductor TMC2301 and
TMC2302 Image Manipulation Sequencers, the TMC2246A
can execute a bilinear interpolation of an image (4-pixel ker-
nels) at real-time video rates. Larger kernels or other, more
complex, functions can be realized with no loss in performance
by utilizing multiple devices.
With unrestricted access to all data and coefficient input
ports, the TMC2246A offers considerable flexibility in appli-
cations performing digital filtering, adaptive FIR filters, mix-
ers, and other similar systems requiring high-speed
processing.
Fabricated in a submicron CMOS process, the TMC2246A
operates at a guaranteed clock rate of 60 MHz over the full
temperature and supply voltage ranges. It is pin- and func-
tion-compatible with CADEKA’s TMC2246, while providing
higher speed operation and lower power dissipation. It is
available in a 120 pin Plastic Pin Grid Array (PPGA), 120
pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to
PPGA (MPGA), and a 120 lead Metric Quad FlatPack
(MQFP).
REV. 1.0.3 9/11/00
Logic Symbol
TMC2246A
Image Filter
D1
9-0
C1
10-0
D2
9-0
C2
10-0
D3
9-0
C3
10-0
D4
9-0
C4
10-0
ENB1-4
ENSEL
ACC
FSEL
S
15-0
OCEN
OEN
CLK
PRODUCT SPECIFICATION
TMC2246A
Block Diagram
D19-0 C110-0 ENB1 D29-0 C210-0 ENB2 D39-0 C310-0 ENB3 D4 9-0 C410-0 ENB4
ENSEL
ACC
FSEL
*
2 -10
25
OCEN
LSB
MSB
CLK
OEN
*Automatic rounding function
S15-0
Functional Description
The TMC2246A Image Filter is a flexible multiplier-summer
array which computes the accumulated sum of four 11x10
bit products, allowing word growth up to 25 bits.
The inputs are user-configurable, allowing latching of either
the 10- or 11-bit input data. The data format is user-selectable
between integer or fractional two’s complement arithmetic.
Total latency from input registers to output data port is 5
clocks.
The output data path is 16 bits wide, providing the lower 16
bits of the accumulator when in integer format or the upper
16 bits of the 25-bit accumulator path when fractional two’s
complement notation is selected. One-time rounding to 16
bits is performed automatically when accumulating frac-
tional data, but is disabled when operating in integer format
to maintain the integrity of the least-significant bits.
2
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number
Pin Name
Power
V
DD
GND
Clock
CLK
C3
1
System Clock.
The TMC2246A operates from a single master
clock input. The rising edge of clock strobes all enabled registers.
All timing specifications are referenced to the rising edge of CLK.
Data Input Ports.
D1 through D4 are the 10-bit data input ports.
The LSB is Dx
0
.
F3, H3, L7, C8
E3, G3, J3, L6,
H11, C7
12, 20, 46, 102
Supply Voltage.
The TMC2246A operates from a single +5V
supply. All power and ground pins must be connected.
8, 16, 24, 42,
72, 106
Ground.
The TMC2246A operates from a single +5V supply. All
power and ground pins must be connected.
CPGA/PPGA/
MPGA
MQFP
Pin Function Description
Inputs
D1
9-0
M1, K3, L2, N1, 27, 28, 29, 30,
L3, M2, N2, L4, 31, 32, 33, 34,
M3, N3
35, 36
J12, K13, J11, 70, 69, 68, 67,
K12, L13, L12, 66, 65, 64, 63,
K11, M13, M12,
62, 61
L11
J13, H12, H13, 71, 73, 74, 75,
G12, G11, G13, 76, 77, 78, 79,
F13, F12, F11,
80, 81
E13
B4, C5, A4, B5, 115, 114, 113,
A5, C6, B6, A6, 112, 111, 110,
A7, B7
109, 108, 107,
105
M4, L5, N4, M5, 37, 38, 39, 40,
N5, M6, N6, M7, 41, 43, 44, 45,
N7, N8, M8
47, 48, 49
N13, M11, L10, 60, 59, 58, 57,
N12, N11, M10, 56, 55, 54, 53,
L9, N10, M9,
52, 51, 50
N9, L8
E12, D13, E11,
D12, C13, B13,
D11, C12, A13,
C11, B12
82, 83, 84, 85,
86, 87, 88, 89,
90, 91, 92
D2
9-0
D3
9-0
D4
9-0
C1
10-0
Coefficient Input Ports.
C1 through C4 are the 11-bit coefficient
input ports. The LSB is Cx
0
.
C2
10-0
C3
10-0
C4
10-0
A8, B8, A9, B9, 104, 103, 101,
A10, C9, B10, 100, 99, 98, 97,
A11, B11, C10, 96, 95, 94, 93
A12
C1, D2, D1, E2, 6, 7, 9, 10, 11,
E1, F2, F1, G2, 13, 14, 15, 17,
G1, H1, H2, J1, 18, 19, 21, 22,
J2, K1, K2, L1
23, 25, 26
Sum Output.
The current 16-bit result is available at the Sum
output. The LSB is S
0
. See the Functional Block Diagram
.
Outputs
S
15-0
REV. 1.0.3 9/11/00
5
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