AS4C16M16MD1
256Mb MOBILE DDR SDRAM
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ...................................................................................................
4
2. FEATURES...........................................................................................................................
4
3. PIN DESCRIPTION...............................................................................................................
5
3.1 Signal Descriptions..........................................................................................................................
6
4. BLOCK DIAGRAM ...............................................................................................................
8
4.1 Block Diagram .................................................................................................................................8
4.2 Simplified State Diagram .................................................................................................................
9
5. FUNCTION DESCRIPTION .................................................................................................10
5.1 Initialization ....................................................................................................................................11
5.1.1 Initialization Flow Diagram .................................................................................................................
12
5.2 Register Definition .........................................................................................................................13
5.2.1 Mode Register ............................................................................................................................
13
5.3 Burst Definition .............................................................................................................................. 13
5.2.1.2 Burst Type ............................................................................................................................... 14
5.2.2 Extended Mode Register............................................................................................................ 14
5.2.2.1 Partial Array Self Refresh ....................................................................................................... 15
5.2.2.2 Temperature Compensated Self Refresh ............................................................................... 15
5.2.2.3 Output Drive Strength ............................................................................................................. 15
6. COMMANDS
.................................................................................................................... 16
7.OPERATION ........................................................................................................................ 21
7.1.
7.2.
7.4.
7.5.
Deselect........................................................................................................................................ 21
No Operation ................................................................................................................................ 21
Active ............................................................................................................................................ 22
Read ............................................................................................................................................. 23
7.5.1 Read to Read ......................................................................................................................................25
6.5.11 Burst Terminate................................................................................................................................. 30
7.6 Write .............................................................................................................................................. 30
7.6.1 Write to Write .....................................................................................................................................32
7.7 Precharge ...................................................................................................................................... 36
7.8 Auto Precharge ............................................................................................................................. 37
7.9 Refresh Requirements .................................................................................................................. 37
7.10 Auto Refresh ............................................................................................................................... 37
7.11 Self Referesh............................................................................................................................... 37
7.12 Power Down ................................................................................................................................ 39
7.13 Deep Power Down ...................................................................................................................... 41
7.14 Clock Stop ................................................................................................................................... 42
8. ELECTRICAL CHARACTERISTIC ......................................................................................43
Confidential
- 1/56 -
Ver.1.1 Oct.2015
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
8.1 Absolute Maximum Ratings ..........................................................................................................43
8.2 Input/Output Capacitance ............................................................................................................. 43
8.3 Electrical Characteristics and AC/DC Operating Conditions ........................................................ 44
8.3.1 Electrical Characteristics and AC/DC Operating Conditions............................................................... 44
8.4 IDD Specification Parameters and Test Conditions ..................................................................... 45
8.4.1 IDD Specification Parameters and Test Conditions ............................................................................ 45
8.5 AC Timings .................................................................................................................................... 47
8.5.2 Output Slew Rate Characteristics .......................................................................................................51
7.5.3 AC Overshoot/Undershoot Specification ............................................................................................. 51
8.5.4 AC Overshoot and Undershoot Definition ........................................................................................... 52
9. PACKAGE DIMENSION ..................................................................................................... 53
10. ORDERING INFORMATION............................................................................................. 54
11. REVISION HISTORY ........................................................................................................ 55
Confidential
- 2/56 -
Ver.1.1 Oct.2015
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
Revision History
256M
AS4C16M16MD1- 60-ball FPBGA
PACKAGE
Revision
Rev 1.0
Rev 1.1
Details
Preliminary datasheet
Temperature Changed
from -25 to -30°C to +85°C
Date
Mar 28,
2013
Oct 24,
2015
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
- 3/56 -
Ver.1.1 Oct.2015
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
1. GENERAL DESCRIPTION
This AS4C16M16MD1 is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,864 bits bank is organized
as 8,192 rows by 512 columns by 16 bits, fabricated with Alliance Memory's high performance CMOS technology. This device uses a
double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating
frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high
bandwidth and high performance memory system applications.
2. FEATURES
•AS4C16M16MD1
VDD/VDDQ = 1.7~1.95V
• Data width: x16
• Clock rate: 200MHz,166MHz , 133MHz
• Partial Array Self-Refresh(PASR)
• Auto Temperature Compensated Self-Refresh(ATCSR)
• Power Down Mode
• Deep Power Down Mode (DPD Mode)
• Programmable output buffer driver strength
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Clock Stop capability during idle periods
• Auto Pre-charge option for each burst access
• Double data rate for data output
• Differential clock inputs (CK and CK )
• Bidirectional, data strobe (DQS)
• CAS Latency: 2 and 3
• Burst Length: 2, 4, 8 and 16
• Burst Type: Sequential or Interleave
• 64 ms Refresh period
• Interface: LVCMOS
• Operating Temperature Range
Extended (-30℃ to + 85
℃)
Table 1. Ordering Information
Part Number
AS4C16M16MD1-6BCN
Clock
rate
166MHz
Package
60-ball FPBGA
(8.0X9.0 mm)
Temperature
Extended
Temp Range
-30°C to +85°C
B: indicates BGA package
C: indicates Extended temp
I: indicates Industrial temp (to follow at a later date)
N: Indicates lead free and ROHS compliant
Confidential
- 4/56 -
Ver.1.1 Oct.2015
AS4C16M16MD1
256Mb MOBILE DDR SDRAM
3. PIN DESCRIPTION
60- Ball FPBGA Assignment
TOP VIEW
2
3
4
5
6
7
8
9
1
A
B
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
VDDQ
DQ13
DQ
14
DQ
1
DQ2
VSSQ
C
D
VSSQ
DQ11
DQ
12
DQ
3
DQ4
VDDQ
VDDQ
DQ9
DQ
10
DQ
5
DQ6
VSSQ
E
F
VSSQ
UDQS
DQ8
DQ
7
LDQS
VDDQ
VSS
UDM
NC
NC
LDM
VDD
G
H
CKE
CK
/CK
/WE
/CAS
/RAS
A9
A11
A12
/CS
BA0
BA1
J
A6
A7
A8
A10/AP
A0
A1
K
VSS
A4
A5
A2
A3
VDD
Figure 1 — PIN DESCRIPTION
Confidential
- 5/56 -
Ver.1.1 Oct.2015
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
