74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
Rev. 06 — 4 May 2009
Product data sheet
1. General description
The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard
input signals. They are capable of transforming slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage V
T+
and the
negative V
T−
is defined as the hysteresis voltage V
H
.
2. Features
I
Balanced propagation delays
I
Inputs accept voltages higher than V
CC
I
Input levels:
N
For 74AHC132: CMOS level
N
For 74AHCT132: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC132
74AHC132D
74AHC132PW
74AHC132BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO14
TSSOP14
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT402-1
SOT762-1
Description
Version
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
Table 1.
Ordering information
…continued
Package
Temperature range Name
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
74AHCT132
74AHCT132D
74AHCT132PW
74AHCT132BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO14
TSSOP14
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
4. Functional diagram
1A
1Y
2
1B
3
1
4
2A
2Y
6
1
2
4
&
3
5
2B
9
3A
3Y
5
8
9
10
&
6
10
3B
&
8
12
4A
4Y
12
11
13
mna408
&
11
13
4B
mna407
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
A
Y
B
mna409
Fig 3.
Logic diagram (one Schmitt trigger)
74AHC_AHCT132_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 4 May 2009
2 of 17
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
5. Pinning information
5.1 Pinning
terminal 1
index area
1B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
mna406
1A V
CC
2
3
4
5
6
7
GND 3Y
8
14
13 4B
12 4A
11 4Y
10 3B
9
3A
001aac439
14 V
CC
13 4B
12 4A
1Y
2A
2B
2Y
132
11 4Y
10 3B
9
8
3A
3Y
GND
(1)
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input A
data input B
data output Y
data input A
data input B
data output Y
ground (0 V)
data output Y
data input A
data input B
data output Y
data input A
data input B
supply voltage
74AHC_AHCT132_6
1
132
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 4 May 2009
3 of 17
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
6. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP14 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly at 4.5 mW/K.
74AHC_AHCT132_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 4 May 2009
4 of 17
NXP Semiconductors
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
8. Recommended operating conditions
Table 5.
74AHC132
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
74AHCT132
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 4.5 V to 5.5 V
4.5
0
0
−40
-
5.0
-
-
+25
-
5.5
5.5
V
CC
+125
20
V
V
V
°C
ns/V
2.0
0
0
−40
-
-
5.0
-
-
+25
-
-
5.5
5.5
V
CC
+125
100
20
V
V
V
°C
ns/V
ns/V
Operating conditions
Conditions
Min
Typ
Max
Unit
Symbol Parameter
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74AHC132
V
OH
HIGH-level
V
I
= V
T+
or V
T−
output voltage
I
O
=
−50 µA;
V
CC
= 2.0 V
I
O
=
−50 µA;
V
CC
= 3.0 V
I
O
=
−50 µA;
V
CC
= 4.5 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
I
O
=
−8.0
mA; V
CC
= 4.5 V
V
OL
LOW-level
V
I
= V
T+
or V
T−
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
1.9
2.9
4.4
2.48
3.80
-
-
-
-
-
-
-
-
2.2
3.15
3.85
-
-
0.1
0.1
0.1
0.44
0.44
1.0
20
10
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
V
V
V
V
V
µA
µA
pF
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
V
I
= V
CC
or GND
74AHC_AHCT132_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 4 May 2009
5 of 17
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
