74ACT715, 74ACT715-R Programmable Video Sync Generator
April 2007
74ACT715, 74ACT715-R
Programmable Video Sync Generator
Features
■
Maximum Input Clock Frequency
>
130MHz
■
Interlaced and non-interlaced formats available
■
Separate or composite horizontal and vertical Sync
■
■
■
■
■
tm
General Description
The ACT715 and ACT715-R are 20-pin TTL-input
compatible devices capable of generating Horizontal,
Vertical and Composite Sync and Blank signals for tele-
visions and monitors. All pulse widths are completely
definable by the user. The devices are capable of gener-
ating signals for both interlaced and noninterlaced
modes of operation. Equalization and serration pulses
can be introduced into the Composite Sync signal when
needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can
be used to generate horizontal or vertical gating pulses,
cursor position or vertical Interrupt signal.
These devices make no assumptions concerning the
system architecture. Line rate and field/frame rate are all
a function of the values programmed into the data regis-
ters, the status register, and the input clock frequency.
The ACT715 is mask programmed to default to a Clock
Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming
before operation.
The ACT715-R is the same as the ACT715 in all
respects except that the ACT715-R is mask pro-
grammed to default to a Clock Enabled state. Bit 10 of
the Status Register defaults to a logic “1”. Although
completely (re)programmable, the ACT715-R version is
better suited for applications using the default
14.31818MHz RS-170 register values. This feature
allows power-up directly into operation, following a single
CLEAR pulse.
and Blank signals available
Complete control of pulse width via register
programming
All inputs are TTL compatible
8mA drive on all outputs
Default RS170/NTSC values mask programmed into
registers
ACT715-R is mask programmed to default to a Clock
Enable state for easier start-up into 14.31818MHz
RS170 timing
Ordering Information
Order Number
74ACT715SC
74ACT715-RSC
Package
Number
M20B
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
74ACT715, 74ACT715-R Programmable Video Sync Generator
Connection Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the
ACT715.
Data Inputs D0–D7:
The Data Input pins connect to the
Address Register and the Data Input Register.
ADDR/DATA:
The ADDR/DATA signal is latched into
the device on the falling edge of the LOAD signal. The
signal determines if an address (0) or data (1) is present
on the data bus.
L/HBYTE:
The L/HBYTE signal is latched into the device
on the falling edge of the LOAD signal. The signal deter-
mines if data will be read into the 8 LSB's (0) or the
4 MSB's (1) of the Data Registers. A 1 on this pin when
an ADDR/DATA is a 0 enables Auto-Load Mode.
LOAD:
The LOAD control pin loads data into the
Address or Data Registers on the rising edge. ADDR/
DATA and L/HBYTE data is loaded into the device on
the falling edge of the LOAD. The LOAD pin has been
implemented as a Schmitt trigger input for better noise
immunity.
CLOCK:
System CLOCK input from which all timing is
derived. The clock pin has been implemented as a
Schmitt trigger for better noise immunity. The CLOCK
and the LOAD signal are asynchronous and indepen-
dent. Output state changes occur on the falling edge of
CLOCK.
CLR:
The CLEAR pin is an asynchronous input that ini-
tializes the device when it is HIGH. Initialization consists
of setting all registers to their mask programmed values,
and initializing all counters, comparators and registers.
The CLEAR pin has been implemented as a Schmitt
trigger for better noise immunity. A CLEAR pulse should
be asserted by the user immediately after power-up to
ensure proper initialization of the registers—even if the
user plans to (re)program the device.
Note:
A CLEAR pulse will disable the CLOCK on the ACT715
and will enable the CLOCK on the ACT715-R.
ODD/EVEN:
Output that identifies if display is in odd
(HIGH) or even (LOW) field of interlace when device is in
interlaced mode of operation. In noninterlaced mode of
operation this output is always HIGH. Data can be seri-
ally scanned out on this pin during Scan Mode.
VCSYNC:
Outputs Vertical or Composite Sync signal
based on value of the Status Register. Equalization and
Serration pulses will (if enabled) be output on the
VCSYNC signal in composite mode only.
VCBLANK:
Outputs Vertical or Composite Blanking
signal based on value of the Status Register.
HBLHDR:
Outputs Horizontal Blanking signal, Horizon-
tal Gating signal or Cursor Position based on value of
the Status Register.
HSYNVDR:
Outputs Horizontal Sync signal, Vertical
Gating signal or Vertical Interrupt signal based on value
of Status Register.
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
2
74ACT715, 74ACT715-R Programmable Video Sync Generator
Logic Block Diagram
Figure 1.
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
3
74ACT715, 74ACT715-R Programmable Video Sync Generator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±15mA
±20mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
V /
∆
t
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate:
Parameter
Rating
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
4
74ACT715, 74ACT715-R Programmable Video Sync Generator
Register Description
All of the data registers are 12 bits wide. Width’s of all
pulses are defined by specifying the start count and end
count of all pulses. Horizontal pulses are specified with
respect to the number of clock pulses per line and verti-
cal pulses are specified with respect to the number of
lines per frame.
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
B9—
B10—
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ACT715
and “1” in the ACT715-R.
Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for
internal testing only.
REG0—Status Register
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
The default value for the Status Register is 0 (000 Hex) for
the ACT715 and is “1024” (400 Hex) for the ACT715-R.
Bits 0–2
B
2
B
1
B
0
0 0 0
(DEFAULT)
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC
VSYNC
VSYNC
CSYNC
CSYNC
VSYNC
VSYNC
HBLANK
HGATE
HBLANK
CUSOR
HBLANK
CUSOR
HBLANK
VGATE
HSYNC
HSYNC
VINT
VINT
HSYNC
HSYNC
VCBLANK VCSYNC
CBLANK
CSYNC
HBLHDR HSYNVDR
HGATE
VGATE
B11—
Horizontal Interval Registers
The Horizontal Interval Registers determine the number
of clock cycles per line and the characteristics of the
Horizontal Sync and Blank pulses.
REG1— Horizontal Front Porch
REG2— Horizontal Sync Pulse End Time
REG3— Horizontal Blanking Width
REG4— Horizontal Interval Width # of Clocks per Line
Vertical Interval Registers
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical
Blank and Sync Pulses.
REG5— Vertical Front Porch
REG6— Vertical Sync Pulse End Time
REG7— Vertical Blanking Width
REG8— Vertical Interval Width # of Lines per Frame
Bits 3–4
B
4
0
B
3
0
Mode of Operation
Interlaced Double Serration and Equalization
(DEFAULT)
0
1
1
1
0
1
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration and Equalization
Equalization and Serration Pulse Specification
Registers
These registers determine the width of equalization and
serration pulses and the vertical interval over which they
occur.
REG 9— Equalization Pulse Width End Time
REG10— Serration Pulse Width End Time
REG11— Equalization/Serration Pulse Vertical Interval
Start Time
REG12— Equalization/Serration Pulse Vertical Interval
End Time
Double Equalization and Serration mode will output
equalization and serration pulses at twice the HSYNC
frequency (i.e., 2 equalization or serration pulses for
every HSYNC pulse). Single Equalization and Serration
mode will output an equalization or serration pulse for
every HSYNC pulse. In Interlaced mode equalization
and serration pulses will be output during the VBLANK
period of every odd and even field. Interlaced Single
Equalization and Serration mode is not possible with this
part.
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A
value of zero in these bit locations indicates an output
pulse active LOW. A value of 1 indicates an active HIGH
pulse.
B5—
B6—
B7—
B8—
VCBLANK Polarity
VCSYNC Polarity
HBLHDR Polarity
HSYNVDR Polarity
Vertical Interrupt Specification Registers
These Registers determine the width of the Vertical
Interrupt signal if used.
REG13— Vertical Interrupt Activate Time
REG14— Vertical Interrupt Deactivate Time
©1988 Fairchild Semiconductor Corporation
74ACT715, 74ACT715-R Rev. 1.3
www.fairchildsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
