Data Sheet No. PD60253
IRS2111(S)PbF
HALF-BRIDGE DRIVER
Features
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
Internally set deadtime
High-side output in phase with input
RoHS compliant
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
(typ.)
Deadtime (typ.)
600 V max.
200 mA / 420 mA
10 V - 20 V
750 ns & 150 ns
650 ns
Description
The IRS2111 is a high voltage, high speed power MOSFET and
IGBT driver with dependent high-side and low-side referenced
output channels designed for half-bridge applications. Propri-
etary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. Logic input is compatible
with standard CMOS outputs. The output drivers feature a high
pulse current buffer stage designed for minimum driver cross-
conduction. Internal deadtime is provided to avoid shoot-through
in the output half-bridge. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high-side con-
figuration which operates up to 600 V.
Packages
8-Lead PDIP
IRS2111PbF
8-Lead SOIC
IRS21111SPbF
Typical Connection
up to 600 V
V
CC
V
CC
IN
V
B
HO
V
S
TO
LOAD
IN
COM
LO
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IRS2111(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 7 through 10.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dV
s
/dt
P
D
Rth
JA
T
J
T
S
T
L
Definition
High-side floating supply voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage
Allowable offset supply voltage transient (Fig. 2)
Package power dissipation @ T
A
≤
+25
°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8 Lead PDIP)
(8 lead SOIC)
(8 lead PDIP)
(8 lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
—
—
—
—
—
—
-55
—
Max.
625 (Note 1)
V
B
+ 0.3
V
B
+ 0.3
25 (Note 1)
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at a 15 V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side and logic fixed supply voltage
Low-side output voltage
Logic input voltage
Ambient temperature
Min.
V
S
+ 10
Note 2
V
S
10
0
0
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
CC
125
Units
V
°C
Note 2: Logic operational for V
S
of -5 V to +600 V. Logic state held for V
S
of -5 V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
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2
IRS2111(S)PbF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, C
L
= 1000 pF and T
A
= 25 °C unless otherwise specified. The dynamic electrical characteristics
are measured using the test circuit shown in Fig. 3.
Symbol
ton
toff
tr
tf
DT
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Deadtime, LS turn-off to HS turn-on &
HS turn-off to LS turn-on
Delay matching, HS & LS turn-on/off
Min. Typ. Max. Units Test Conditions
550
—
—
—
480
—
750
150
75
35
650
30
950
180
130
65
820
—
ns
V
S
= 0 V
V
S
= 600 V
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V and T
A
= 25 °C unless otherwise specified. The V
IN
, V
TH,
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
Definition
Logic “1” input voltage for HO & logic “0” for LO
Min. Typ. Max. Units Test Conditions
6.4
9.5
12.6
—
—
—
—
—
—
—
0.05
0.02
—
50
70
30
—
8.6
8.2
8.6
8.2
290
—
—
—
3.8
6.0
8.3
0.2
0.1
50
100
180
50
5.0
9.6
9.2
9.6
9.2
—
mA
V
O
= 0 V, V
IN
= V
CC
PW
≤
10 µs
V
O
= 15 V, V
IN
= 0 V
PW
≤
10 µs
V
µA
V
IN
= 0 V or V
CC
V
IN
= V
CC
V
IN
= 0 V
V
V
CC
= 10 V
V
CC
= 15 V
V
CC
= 20 V
V
CC
= 10 V
V
CC
= 15 V
V
CC
= 20 V
I
O
= 2 mA
V
B
= V
S
= 600 V
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Logic “0” input voltage for HO & logic “1” for LO
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
BS
supply undervoltage positive going threshold
V
BS
supply undervoltage negative going threshold
V
CC
supply undervoltage positive going threshold
V
CC
supply undervoltage negative going threshold
Output high short circuit pulsed current
—
—
—
—
—
—
—
—
—
7.6
7.2
7.6
7.2
200
Output low short circuit pulsed current
420
600
—
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3
IRS2111(S)PbF
Functional Block Diagram
V
B
UV
DETECT
DEAD
TIME
PULSE
GEN
IN
UV
DETECT
HV
LEVEL
SHIFT
R
Q
R
S
V
S
HO
PULSE
FILTER
V
CC
LO
DEAD
TIME
COM
Lead Definitions
Symbol Description
IN
V
B
HO
V
S
V
CC
LO
COM
Logic input for high-side and low-side gate driver outputs (HO & LO), in phase with HO
High-side floating supply
High-side gate drive output
High-side floating supply return
Low-side and logic fixed supply
Low-side gate drive output
Low-side return
Lead Assignments
8 Lead DIP
8 Lead SOIC
IRS2111
Part Number
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IRS2111S
4
IRS2111(S)PbF
IN
HO
LO
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
IN
(LO)
50%
50%
IN
(HO)
ton
tr
90%
toff
90%
tf
LO
HO
Figure 3. Switching Time Test Circuit
10%
10%
Figure 4. Switching Time Waveform Definition
50%
50%
IN
(LO)
50%
50%
IN
IN
(HO)
90%
LO
HO
10%
HO
LO
90%
10%
DT
MT
MT
90%
10%
Figure 5. Deadtime Waveform Definitions
LO
HO
Figure 6. Delay Matching Waveform Definitions
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