AS4C16M16SA-C&I
Revision History
Revision
Rev 1.0
Rev 2.0
Rev 3.0
Details
Preliminary datasheet
Correct some typing mistakes.
1. Add AS4C16M16SA-6TCN part.
2. Modify ordering information.
3. Add part number system on the last page.
Date
February 2014
March 2014
March 2015
Alliance Memory Inc.
511 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800
FAX: (650) 620-9211
Alliance Memory Inc.
reserves the right to change products or specification without notice.
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Rev. 3.0
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AS4C16M16SA-C&I
256M – (16Mx16bit) Synchronous DRAM (SDRAM)
Confidential
Features
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
4M word x 16-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
Operating temperature range
- Commercial (0 ~ 70°
C)
- Industrial (-40 ~ 85°
C)
Auto Refresh and Self Refresh
8192 refresh cycles/64ms
CKE power down mode
Single +3.3V
±
0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package
- All parts ROHS are compliant
Advanced(Rev. 3.0, Mar. /2015)
Overview
256Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 256 Mbits. It is
internally configured as 4 Banks of 4M word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications.
T
he
Table 1. Key Specifications
AS4C16M16SA
tCK3
Clock Cycle time (min.)
tAC3
Access time from CLK (max.)
tRAS
Row Active time (min.)
tRC
Row Cycle time (min.)
Table 2. Ordering Information
Part Number
Frequency
AS4C16M16SA-7TCN
143 MHz
AS4C16M16SA-6TCN
166 MHz
AS4C16M16SA-6TIN
166 MHz
AS4C16M16SA-7BCN
143 MHz
AS4C16M16SA-6BIN
166 MHz
T : indicates TSOP II package
B : indicates TFBGA package
C: Commercial I: Industrial
N : indicates Pb free and Halogen free
-6/7
6/7 ns
5/5.4 ns
42/42 ns
60/63 ns
Package
54 pin TSOP II
54 pin TSOP II
54 pin TSOP II
54 ball TFBGA
54 ball TFBGA
Temperature
Commercial
Commercial
Industrial
Commercial
Industrial
Temp Range
0~70℃
0~70℃
-40~85℃
0~70℃
-40~85℃
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AS4C16M16SA-C&I
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE#
CAS#
RAS#
CS#
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Figure 1.1 Ball Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
…
7
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS#
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS#
BA1
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
VDD
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AS4C16M16SA-C&I
Figure 2. Block Diagram
Row
Decoder
CLK
CKE
CLOCK
BUFFER
4M x 16
CELL ARRAY
(BANK #A)
Column Decoder
CS#
RAS#
CAS#
WE#
DQ0
COMMAND
DECODER
Buffer
CONTROL
SIGNAL
GENERATOR
DQ15
LDQM, UDQM
Row
Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
4M x 16
CELL ARRAY
(BANK #B)
Column Decoder
A0
A9
A11
A12
BA0
BA1
~
ADDRESS
BUFFER
Row
Decoder
REFRESH
COUNTER
4M x 16
CELL ARRAY
(BANK #C)
Column Decoder
Row
Decoder
4M x 16
CELL ARRAY
(BANK #D)
Column Decoder
Pin Descriptions
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AS4C16M16SA-C&I
Table 3. Pin Details
Symbol
CLK
Type
Input
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock (set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. When all banks are in the idle state,
deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh
modes, where CKE becomes asynchronous until exiting the same mode. The input
buffers, including CLK, are disabled during Power Down and Self Refresh modes,
providing low standby power.
Bank Activate:
BA0, BA1 input select the bank for operation.
BA1
0
0
1
1
A0-A12
Input
BA0
0
1
0
1
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
CKE
Input
BA0,BA1
Input
Address Inputs:
A0-A12 are sampled during the BankActivate command (row address
A0-A12) and Read/Write command (column address A0-A8 with A10 defining Auto
Precharge) to select one location out of the 4M available in the respective bank. During
a Precharge command, A10 is sampled to determine if all banks are to be precharged
(A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set
command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of the
command code.
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either
the BankActivate command or the Precharge command is selected by the WE# signal.
When the WE# is asserted "HIGH," the BankActivate command is selected and the
bank designated by BA is turned on to the active state. When the WE# is asserted
"LOW," the Precharge command is selected and the bank designated by BA is switched
to the idle state after the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS# "LOW." Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH."
Write Enable:
The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask:
Controls output buffers in read mode and masks
Input data in write mode.
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM,
UDQM
Input
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Rev. 3.0
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