AS4C2M32D1A-5BCN
AS4C2M32D1A-5BIN
Features
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•
•
•
•
•
•
•
Fast clock rate: 200 MHz
Differential Clock CK &
CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 512K x 32-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
4096 refresh cycles / 64ms
Precharge & active power down
Operating Temperature:
Overview
The 64Mb DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 64 Mbits.
It is internally configured as a quad 512K x 32 DRAM
with a synchronous interface (all signals are registered
on the
positive edge of the clock signal, CK).
Data outputs occur at both rising edges of CK and
CK
.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command. The device
provides programmable Read or Write burst lengths of 2,
4, or 8. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the
end of the burst sequence. The refresh functions, either
Auto or Self Refresh are easy to use. In addition, 64Mb
DDR features programmable DLL option. By having a
programmable mode register and extended mode register,
the system can choose the most suitable modes to
maximize its performance. These devices are well suited
for applications requiring high memory bandwidth; result in
a device particularly well suited to high performance main
memory and graphics applications.
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- Commercial (0 ~ 70 °C)
- Industrial (-40 ~ 85 °C)
•
Power supplies: V
DD &
V
DDQ
= 2.5V
±
0.2V
•
Interface: SSTL_2 I/O Interface
•
144-ball 12 x 12 x 1.4mm FBGA package
- Pb and Halogen Free
Table
1.
Ordering Information
Product part No
AS4C2M32D1A-5BCN
AS4C2M32D1A-5BIN
Org
2Mx
32
2Mx
32
Temperature
Commercial
0°C to
70°C
Industrial -40°C
to
85°C
Max Clock (MHz)
200
200
Package
144-ball
FBGA
144-ball
FBGA
Confidential
2 of 63
Rev.1.0 Dec 2015
AS4C2M32D1A-5BCN
AS4C2M32D1A-5BIN
Ball Descriptions
Table
3.
Ball Details
Symbol
CK,
CK
Type
Input
Description
Differential Clock:
CK and
CK
are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative edge of
CK
.
Input and output data is referenced to the crossing of CK and
CK
(both directions of the
crossing)
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
low synchronously with clock, the internal clock is suspended from the next clock cycle and
the state of output and burst address is frozen as long as the CKE remains low. When all
banks are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes.
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs:
A0-A10 are sampled during the Bank Activate command (row address
A0-A10) and Read/Write command (column address A0-A7 with A10 defining Auto
Precharge) to select one location out of the 512K available in the respective bank. During a
Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 =
HIGH). The address inputs also provide the op-code during a Mode Register Set or
Extended Mode Register Set command.
Chip Select:
CS
enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when
CS
is sampled HIGH.
CS
provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
Row Address Strobe:
The
RAS
signal defines the operation commands in conjunction
with the
CAS
and
WE
signals and is latched at the positive edges of CK. When
RAS
and
CS
are asserted "LOW" and
CAS
is asserted "HIGH" either the BankActivate command or
the Precharge command is selected by the
WE
signal. When the
WE
is asserted "HIGH"
the BankActivate command is selected and the bank designated by BA is turned on to the
active state. When the
WE
is asserted "LOW" the Precharge command is selected and the
bank designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe:
The
CAS
signal defines the operation commands in conjunction
with the
RAS
and
WE
signals and is latched at the positive edges of CK. When
RAS
is
held "HIGH" and
CS
is asserted "LOW" the column access is started by asserting
CAS
"LOW". Then, the Read or Write command is selected by asserting
WE
"HIGH" or "LOW".
Write Enable:
The
WE
signal defines the operation commands in conjunction with the
RAS
and
CAS
signals and is latched at the positive edges of CK. The
WE
input is used
to select the BankActivate or Precharge command and Read or Write command.
Bidirectional Data Strobe:
The DQSx signals are mapped to the following data bytes:
DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, DQS3 to DQ24-DQ31.
Data Input Mask:
DM0-DM3 are byte specific. Input data is masked when DM is sampled
HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-DQ16, DM1 masks
DQ15-DQ8, and DM0 masks DQ7-DQ0.
Data I/O:
The DQ0-DQ31 input and output data are synchronized with positive and
negative edges of DQS0~DQS3. The I/Os are byte-maskable during Writes.
Power Supply:
2.5V
±
0.2V.
Ground
DQ Power:
2.5V
±
0.2V . Provide isolated power to DQs for improved noise immunity.
CKE
Input
BA0, BA1
A0-A10
Input
Input
CS
Input
RAS
Input
CAS
Input
WE
Input
DQS0-DQS3
Input /
Output
DM0 - DM3
Input
DQ0 - DQ31
V
DD
V
SS
V
DDQ
Input /
Output
Supply
Supply
Supply
Confidential
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Rev.1.0 Dec 2015
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