CTSLV394
MLP8
LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs
FEATURES
Selectable Divide Ratio
Selectable Enable Priority and Threshold
(CMOS or PECL)
Tristate Compatible Outputs
Input Buffer Powers Down when Disabled
High BW [1.5GHz (÷1), 3.0GHz (÷2)]
3V to 5.5V Power Supply
-145dBc/Hz (÷1) Typ Noise Floor
-151dBc/Hz (÷2) Typ Noise Floor
RoHS Compliant Pb Free Packages
BLOCK DIAGRAM
DESCRIPTION
The CTSLV394 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or
Pierce based oscillators. The tri-state compatible outputs allow for on-the-fly switching of multiple
oscillators on a common bus. Other features are incorporated to reduce board components. A voltage
reference and input biasing allows for easy oscillator interface.
The CTSLV394 provides a ÷ 2 mode of operation for more frequency options and is selectable with a
single connection. A selectable enable is also provided which doubles as a reset when the CTSLV394 is in
÷2 mode. With a single connection, the enable can be selected to operate as active high or active low.
ENGINEERING NOTES
The CTSLV394 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The
divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the CTSLV394 functions
as a standard receiver. If DIV-SEL is connected to V
EE
, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC),
V
EE
, or connected to V
EE
via a 20k ± 20% resistor. Leaving EN-SEL open or connecting it to V
EE
allows
the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75k
pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is
connected to V
EE
, an internal 75k pull-down resistor is selected which disables the outputs whenever EN
is left open.
Connecting the EN-SEL to V
EE
with a 20k resistor will allow the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75k pull-down resistor. In this mode, outputs are enabled when EN is
left open (NC). The default logic condition can be overridden by connecting the EN to V
CC
with an external
resistor of
20k.
If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL
connected to V
EE
with a 20k resistor), the EN pin/pad voltage swing must be reduced using two external
resistors. Contact the factory for details.
When the CTSLV394 is disabled, the Q and Q outputs are forced LOW and the input buffer is powered
¯
down to minimize feed through. This feature allows tri-state compatible parallel output connections.
Multiple CTSLV394 chip outputs can be wired together. Since both outputs are forced LOW in the disable
mode, an enabled CTSLV394 can drive the output lines without interference from the unselected units. In
addition, the CTSLV394 can be used in parallel connection with PECL/ECL parts whose outputs are high
impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter
resets when the outputs are disabled.
The CTSLV394 provides a V
BB
with an 1880 internal bias resistor from D to V
BB
. This feature allows AC
coupling with minimal external components. The V
BB
pin supports 1.5mA sink/source current and should
be bypassed to ground or V
CC
with a 0.01
F
capacitor.
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice
1
RevA1113
CTSLV394
MLP8
LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
V
CC
V
I_PECL
V
EE
V
I_ECL
I
HGOUT
T
A
T
STG
ESD
HBM
ESD
MM
ESD
CDM
Characteristic
PECL Power Supply
PECL Input Voltage
ECL Power Supply
ECL Input Supply
Output Current
Operating Temperature Range
Storage Temperature Range
Human Body Model Electro Static Discharge
Machine Model Electro Static Discharge
Charged Device Model Electro Static Discharge
Condition
V
EE
= 0V
V
EE
= 0V
V
CC
= 0V
V
CC
= 0V
Continuous
Surge
-
-
-
-
-
Rating
0 to + 6.0
0 to + 6.0
-6.0 to 0
-6.0 to 0
50
100
-40 to +85
-65 to +150
2500
200
2000
Unit
V
V
V
V
mA
°C
°C
V
V
V
100K ECL DC Characteristics (V
EE
= -3.0V to -5.5V, V
CC
= GND)
Symbol
V
OH
V
OL
V
IH
Characteristic
Output HIGH Voltage
1
Output LOW Voltage
1
Input HIGH Voltage
D,EN (ECL)
2
Input HIGH Voltage EN
(CMOS)
3
Input LOW Voltage
D,EN (ECL)
2
Input LOW Voltage EN
(CMOS)
3
Reference Voltage
Input HIGH Current EN
Input LOW Current EN
(ECL)
2
Input LOW Current EN
(CMOS)
3
Power Supply Current
1
1
2
3
-40°C
Min
-1085
-1900
-1165
V
EE
+2000
-1900
V
EE
-1390
0.5
-150
34
Max
-880
-1555
-740
V
CC
-1475
V
EE
+800
-1250
150
0.5
-150
Min
-1025
-1900
-1165
0°C
Max
-880
-1620
-740
V
CC
-1475
V
EE
+800
-1250
150
0.5
-150
34
Min
25°C
Max
-880
-1620
-740
V
CC
-1475
V
EE
+800
-1250
150
0.5
Min
-1025
-1900
-1165
V
EE
+2000
-1900
V
EE
-1390
85°C
Max
-880
-1620
-740
V
CC
-1475
V
EE
+800
-1250
150
-1025
-1900
-1165
V
EE
+2000
-1900
V
EE
-1390
Unit
mV
mV
mV
mV
mV
mV
mV
µA
µA
V
EE
+2000
-1900
V
EE
-1390
V
IL
V
BB
I
IH
I
IL
I
EE
-150
34
37
mA
Specified with each output terminated through 50Ω resistors to V
CC
-2V.
EN-SEL connected to V
EE
through a 20kΩ resistor.
EN-SEL connected to V
EE
or left open (NC).
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice
2
RevA1113
CTSLV394
MLP8
LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs
100K LVPECL DC Characteristics (V
EE
= GND, V
CC
= +3.3V)
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
1
2
3
4
Characteristic
Output HIGH Voltage
1,2
Output LOW Voltage
1,2
Input HIGH Voltage D,EN (ECL)
3
Input HIGH Voltage EN (CMOS)
Input LOW Voltage D,EN (ECL)
Reference Voltage
1
Input HIGH Current EN
Input LOW Current EN (ECL)
3
Input LOW Current EN (CMOS)
4
Power Supply Current
2
4
3
-40°C
Min
Max
2215
2420
1400
2135
2000
1400
GND
1910
0.5
-150
34
1745
2560
V
CC
1825
800
2050
150
0°C
Min
Max
2275
2420
1400
2135
2000
1400
GND
1910
0.5
-150
34
1680
2560
V
CC
1825
800
2050
150
25°C
Min
Max
2275 2420
1400
2135
2000
1400
GND
1910
0.5
-150
34
1680
2560
V
CC
1825
800
2050
150
85°C
Min
Max
2275
2420
1400
2135
2000
1400
GND
1910
0.5
-150
37
1680
2560
V
CC
1825
800
2050
150
Unit
mV
mV
mV
mV
mV
mV
mV
µA
µA
mA
Input LOW Voltage EN (CMOS)
4
For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value.
Specified with each output terminated through 50Ω resistors to V
CC
-2V.
EN-SEL connected to V
EE
through a 20kΩ resistor.
EN-SEL connected to V
EE
or left open (NC).
100K PECL DC Characteristics (V
EE
= GND, V
CC
= +5.0V)
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
1
2
3
4
Characteristic
Output HIGH Voltage
1,2
Output LOW Voltage
1,2
Input HIGH Voltage D,EN (ECL)
3
Input HIGH Voltage EN (CMOS)
4
Input LOW Voltage D,EN (ECL)
3
Input LOW Voltage EN (CMOS)
4
Reference Voltage
1
Input HIGH Current EN
Input LOW Current EN (ECL)
3
Input LOW Current EN (CMOS)
4
Power Supply Current
2
-40°C
Min
Max
3915
4120
3100
3445
3835
4260
2000
V
CC
3100
3525
GND
800
3610
3750
150
0.5
-150
34
0°C
Min
3975
3100
3835
2000
3100
GND
3610
0.5
-150
34
Max
4120
3380
4260
V
CC
3525
800
3750
150
25°C
Min
Max
3975
4120
3100
3380
3835
4260
2000
V
CC
3100
3525
GND
800
3610
3750
150
0.5
-150
34
85°C
Min
Max
3975 4120
3100 3380
3835 4260
2000
V
CC
3100 3525
GND
800
3610 3750
150
0.5
-150
37
Unit
mV
mV
mV
mV
mV
mV
mV
µA
µA
mA
For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value.
Specified with each output terminated through 50Ω resistors to V
CC
-2V.
EN-SEL connected to V
EE
through a 20kΩ resistor.
EN-SEL connected to V
EE
or left open (NC).
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice
3
RevA1113
CTSLV394
MLP8
LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs
AC Characteristics (V
EE
= -3.0V to -5.5V; V
CC
=GND or V
EE
=GND; V
CC
= +3.0V to +5.5V)
Symbol
Characteristic
D to Q/Q
1
¯
t
PLH
/t
PHL
t
SKEW
V
PP
(AC)
t
R
/t
F
1
2
3
4
-40°C
Min
Typ
Max
450
3000
5
150
100
20
1000
240
150
100
Min
0°C
Typ
Max
450
3000
5
20
1000
240
150
100
Min
25°C
Typ
Max
450
3000
5
20
1000
240
150
100
Min
85°C
Typ
Max
450
3000
5
20
1000
240
Unit
ps
ps
ps
mV
ps
EN to
Q
HG
/Qb
HG1,2
Duty Cycle
Skew
3
Input Swing
4
Output Rise/Fall
1
(20% - 80%)
Specified with each output terminated through 50Ω resistors to V
CC
-2V.
Specified from 50% EN input edge to V
OH
min to V
OL
max of the Q/Q outputs.
¯
Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
V
PP
is the peak-to-peak differential input swing for which AC parameters are guaranteed.
Tri-state Compatible Operation
The outputs of the CTSLV394 are emitter followers as shown in the left side of Figure 1. When a part is
disabled, both outputs are set in the LOW state. This allows a HIGH output from an enabled part to override a
disabled output and pull the combined line HIGH as seen in the right hand side of Figure 1. When the enabled
part output is LOW, the combined line remains LOW. If all connected CTS94 parts are disabled, both output
lines will be in the LOW state. As another feature, while disabled, the input buffer is powered down to
minimize feed through.
CTSLV394 Transistor
Output Stage
Figure 1: Typical Tri-state Operation
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice
4
RevA1113
CTSLV394
MLP8
LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs
Divide Truth Table
DIV-SEL
NC
V
EE1
1
÷Ratio
÷1
÷2
DIV-SEL connection must be
≤1W.
Enable Truth Table
EN-SEL
NC
V
EE
20kΩ to V
EE
EN
CMOS Low or V
EE
CMOS High, V
CC
or NC
CMOS Low, V
EE
or NC
CMOS High or V
CC
PECL Low, V
EE
or NC
PECL High or V
CC
Q
Low
Data
Low
Data
Low
Data
Q
¯
Low
Data
Low
Data
Low
Data
Figure 2 illustrates the timing sequences for the CTSLV394 in the ÷1 mode which is determined by leaving
the DIV-SEL open (NC). It also illustrates the enable in the active High mode being controlled by a CMOS
signal. This mode is determined by leaving the EN-SEL open (NC).
Figure 2
Figure 3 illustrates the timing sequences for the CTSLV394 in the ÷2 mode which is determined by
connecting the DIV-SEL to V
EE
. It also illustrates the enable in the active Low mode being controlled by a
PECL signal. This mode is determined by connecting the EN-SEL to V
EE
via 20kΩ resistor.
Figure 3
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice
5
RevA1113
Microchip MCU
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