Low Skew, ÷1, ÷2
Clock Generator
Data Sheet
8701I
G
ENERAL
D
ESCRIPTION
The 8701I is a low skew, ÷1, ÷2 Clock Generator. The
low impedance LVCMOS outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 20 to 40 by utilizing the
ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable in-
puts, BANK_EN0:1, support enabling and disabling each bank
of outputs individually. The master reset input, nMR/OE, resets
the internal frequency dividers and also controls the active and
high impedance states of all outputs.
The 8701I is characterized at 3.3V and mixed 3.3V input supply,
and 2.5V output supply operating modes. Guaranteed bank,
output and part-to-part skew characteristics make the 8701I
ideal for those clock distribution applications demanding well
defined performance and repeatability.
F
EATURES
• Twenty LVCMOS outputs, 7Ω typical output impedance
• LVCMOS / LVTTL clock input
• Maximum input frequency: 250MHz
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• Bank skew: 200ps
• Output skew: 250ps
• Multiple frequency skew: 300ps
• Part-to-part skew: 600ps
• 3.3V or mixed 3.3V input, 2.5V output operating supply
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
• Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision C January 22, 2016
8701I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
2, 5, 11,
26, 32, 35, 41,
44
7, 9, 18, 21,
28, 30, 37, 39,
46, 48
16, 20
25, 27, 29,
31, 33
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
10, 12
22
Name
V
DDO
Power
Type
Description
Output supply pins.
GND
V
DD
QA0, QA1, QA2,
QA3, QA4
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
CLK
Power
Power
Power supply ground.
Positive supply pins.
Bank A outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank B outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank C outputs.LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Bank D outputs. LVCMOS / LVTTLinterface levels.
Output
7Ω typical output impedance.
Input Pulldown LVCMOS / LVTTL clock input.
Controls frequency division for Bank D outputs.
13
DIV_SELD
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank C outputs.
14
DIV_SELC
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank B outputs.
23
DIV_SELB
Input
Pullup
LVCMOS / LVTTLinterface levels.
Controls frequency division for Bank A outputs.
24
DIV_SELA
Input
Pullup
LVCMOS / LVTTLinterface levels.
BANK_EN1,
Enables and disables outputs by banks.
17, 19
Input
Pullup
LVCMOS / LVTTLinterface levels.
BANK_EN0
Master Reset and output enable. When HIGH, output drivers are
15
nMR/OE
Input
Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset.
LVCMOS / LVTTLinterface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc
2
Revision C January 22, 2016
8701I Data Sheet
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DD
, V
DDO
= 3.465V
7
Test Conditions
Minimum
Typical
4
51
51
15
Maximum
Units
pF
kΩ
kΩ
pF
Ω
T
ABLE
3. F
UNCTION
T
ABLE
nMR/OE
0
1
1
1
1
1
1
1
1
Inputs
BANK_EN1 BANK_EN0
X
X
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
DIV_SELx
X
0
0
0
0
1
1
1
1
QA0:QA4
Hi Z
Active
Active
Active
Active
Active
Active
Active
Active
QB0:QB4
Hi Z
Hi Z
Active
Active
Active
Hi Z
Active
Active
Active
Outputs
QC0:QC4
Hi Z
Hi Z
Hi Z
Active
Active
Hi Z
Hi Z
Active
Active
QD0:QD4
Hi Z
Hi Z
Hi Z
Hi Z
Active
Hi Z
Hi Z
Hi Z
Active
Qx frequency
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
fIN
fIN
fIN
©2016 Integrated Device Technology, Inc
3
Revision C January 22, 2016
8701I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
100
Units
V
V
V
mA
©2016 Integrated Device Technology, Inc
4
Revision C January 22, 2016
8701I Data Sheet
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
CLK
V
DD
=
VIN
= 3.465V
V
DD
=
VIN
= 3.465V
V
DD
= 3.465V,
VIN
= 0V
V
DD
= 3.465V,
VIN
= 0V
V
DD
= V
DDO
= 3.135V
I
OH
= -36mA
V
OH
Output High Voltage
V
DD
= 3.135V,
V
DDO
= 2.375
I
OH
= -27mA
V
DD
= V
DDO
= 3.135V
I
OL
= 36mA
V
OL
Output Low Voltage
V
DD
= 3.135V,
V
DDO
= 2.375
I
OL
= 27mA
-150
-5
2.6
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
IH
Input
High Voltage
V
IL
Input
Low Voltage
I
IH
Input
High Current
I
IL
Input
Low Current
1.8
V
0.5
V
0.5
V
©2016 Integrated Device Technology, Inc
5
Revision C January 22, 2016
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