NJW4185
High Voltage Io=500mA Low Dropout Regulator
GENERAL DESCRIPTION
The NJW4185 is a high voltage and low current consumption
low
dropout
regulator.
It has two product type: A version (built-in ON/OFF function type)
and B version (3-terminal / compatible with 78M series)
NJW4185 is mounted to TO-252-3/-5 packages and corresponded to
Low ESR capacitor (MLCC).
The wide input range makes NJW4185 suitable for Automotive
applications, Industrial supplies, Multiple cell battery equipment and
various applications.
PACKAGE OUTLINE
NJW4185DL3
NJW4185DL1
FEATURES
Wide Operating Voltage Range
Low Current Consumption
High Precision Output
Output Current
Output Voltage Range
Correspond to Low ESR capacitor (MLCC)
ON/OFF Function (apply only the A ver.)
Internal Thermal Overload Protection
Internal Over Current Protection
Package Outline
4.0V to 40V
55μA typ. (A version)
48μA typ. (B version)
V
O
1.0%
I
O
(min.)=500mA
2.0V to 15.0V
A version: TO-252-5
B version: TO-252-3
PRODUCT CLASSIFICATION
ON/OFF
Function
NJW4185DL3-xxA
A
Yes
NJW4185DL1-xxB
B
-
xx=Output Voltage ex) 33=3.3V 05=5.0V
Device Name
Version
Package
TO-252-5
TO-252-3
PIN CONFIGURATION
5
4
3
2
1
V
OUT
NC
GND
CONTROL
V
IN
3 V
OUT
2
2 GND
1 V
IN
3
NJW4185DL3-A
NJW4185DL1-B
Ver.2015-12-01
-1-
NJW4185
BLOCK DIAGRAM
½A
version
V
IN
Current
Limit
V
OUT
CONTROL
Bandgap
Reference
Thermal
Protection
GND
½B
version
V
IN
V
OUT
Current
Limit
Bandgap
Reference
Thermal
Protection
GND
OUTPUT VOLTAGE RANK LIST
・A
version
Device Name
Output Voltage
NJW4185DL3-33A
3.3V
NJW4185DL3-05A
5.0V
NJW4185DL3-08A
8.0V
NJW4185DL3-15A
15.0V
・B
version
Device Name
NJW4185DL1-33B
NJW4185DL1-05B
NJW4185DL1-08B
NJW4185DL1-15B
Output Voltage
3.3V
5.0V
8.0V
15.0V
-2-
Ver.2015-12-01
NJW4185
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYNBOL
Input Voltage
V
IN
Control Voltage(*1)
V
CONT
Output Voltage
V
OUT
Power Dissipation
Junction Temperature
Operating Temperature
Storage Temperature
P
D
Tj
Topr
Tstg
RATINGS
-0.3 to +45
-0.3 to +45
-0.3 to V
IN
+17
1190 (*2)
3125 (*3)
-40 to +150
-40 to +125
-40 to +150
(Ta=25 C)
UNIT
V
V
V
mW
C
C
C
(*1): Apply only the A version.
2
(*2): Mounted on glass epoxy board. (76.2 114.3 1.6mm:based on EIA/JDEC standard size, 2Layers, Cu area 100mm )
(*3): Mounted on glass epoxy board. (76.2 114.3 1.6mm:based on EIA/JDEC standard, 4Layers)
(For 4Layers: Applying 74.2 x 74.2mm inner Cu area and thermal via hole to a board based on JEDEC standard JESD51-5)
INPUT VOLTAGE RANGE
V
IN
=4.0V to 40V
ELECTRICAL CHARACTERISTICS
PARAMETER
Output Voltage
Quiescent Current
Quiescent Current
at Control OFF (*4)
SYMBOL
V
O
I
Q
I
Q (OFF)
Unless otherwise noted, V
IN
=V
O
+1V, C
IN
=1.0μF, C
O
=2.2μF, Ta=25 C
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
I
O
=30mA
A version, I
O
=0mA, except I
CONT
B version, I
O
=0mA
V
CONT
=0V
-1.0%
-
-
-
-
55
48
-
+1.0%
90
83
1
V
μA
μA
Output Current
Line Regulation
Load Regulation
I
O
V
O
/ V
IN
V
O
/ I
O
V
O
0.9
V
IN
= V
O
+1V to 40V, I
O
=30mA
I
O
=0mA to 500mA
V
O
=3.3V
V
O
=5.0V
V
O
=8.0V
V
O
=15V
500
-
-
-
-
-
-
-
-
-
-
62
60
55
50
0.27
50
1
-
-
-
0.03
0.006
-
-
-
-
0.42
-
3
-
0.6
mA
%/V
%/mA
Ripple Rejection
RR
V
IN
= V
O
+1V ,ein=200mVrms,
f=1kHz, I
O
=10mA
dB
Dropout Voltage (*5)
Average Temperature
Coefficient of Output Voltage
Control Current (*4)
Control Voltage
for ON-state (*4)
Control Voltage
for OFF-state (*4)
V
I O
I
O
=300mA
V
ppm/ C
μA
V
V
V
O
/ Ta
I
CONT
V
CONT(ON)
V
CONT(OFF)
Ta =0 to 85 C, I
O
=30mA
V
CONT
=1.6V
-
-
1.6
-
(*4):
Apply only the A version.
(*5): Except Output Voltage Rank less than 3.8V
The above specification is a common specification for all output voltages.
Therefore, it may be different from the individual specification for a specific output voltage.
Ver.2015-12-01
-3-
NJW4185
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
Junction-to-Ambient
ja
thermal resistance
Junction-to-Top of package
jt
characterization parameter
VALUE
105 (*6)
40 (*7)
17 (*6)
12 (*7)
UNIT
C/W
C/W
2
(*6): Mounted on glass epoxy board. (76.2 114.3 1.6mm:based on EIA/JDEC standard size, 2Layers, Cu area 100mm )
(*7): Mounted on glass epoxy board. (76.2 114.3 1.6mm:based on EIA/JDEC standard, 4Layers)
(For 4Layers: Applying 74.2 74.2mm inner Cu area and a thermal via hole to a board based on JEDEC standard JESD51-5)
POWER DISSIPATION vs. AMBIENT TEMPERATURE
NJW4185DL1/DL3 PowerDissipation
(Topr=-40~+125°C,Tj=150°C)
3500
3000
Power Dissipation P
D
(mW)
on 4 layers board
2500
2000
1500
1000
500
0
-50
-25
0
25
50
75
100
125
150
on 2 layers board
Temperature : Ta( C)
-4-
Ver.2015-12-01
NJW4185
TEST CIRCUIT
½A
version
A
V
IN
I
IN
V
IN
V
OUT
2.2μF
(Ceramic)
1.0μF
NJW4185-A
I
OUT
V
V
OUT
A
V
V
CONT
I
CONT
CONTROL
GND
½B
version
A
V
IN
I
IN
V
IN
V
OUT
2.2 F
1.0 F
NJW4185-B
I
OUT
V
V
OUT
(ceramic)
GND
Ver.2015-12-01
-5-
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
