FemtoClock
®
NG 12-Output
Frequency Synthesizer
8T49N1012
Datasheet
Description
The 8T49N1012 has one fractional-feedback PLL that can be used
for frequency synthesis. It is equipped with two integer and eight
fractional output dividers, allowing the generation of up to ten different
output frequencies, ranging from 8kHz to 1GHz. Eight of these
frequencies are completely independent of each other and the inputs.
Two more are related frequencies. The twelve outputs may select
among LVPECL, LVDS, HSCL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency synthesis
application, including 1G, 10G, 40G and 100G Synchronous Ethernet,
OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The device supports Output Enable inputs and Lock and LOS status
outputs.
The device is programmable through an I
2
C interface. It also supports
I
2
C master capability to allow the register configuration to be read
from an external EEPROM.
Features
•
•
•
•
<350fs RMS typical jitter (including spurs), @122.88MHz (12kHz
to 20MHz)
Operating modes: locked to input signal and free-run
Operates from a 10MHz to 40MHz fundamental-mode crystal
Accepts one LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input
clock
•
Accepts frequencies ranging from 10MHz up to 600MHz
•
Clock input monitoring
Generates 12 LVPECL / LVDS / HSCL or 24 LVCMOS output
clocks
•
Output frequencies ranging from 8kHz up to 1.0GHz (Q[8:11],
Differential)
•
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Two Output Enable control inputs
Lock and Loss-of-Signal status outputs
Programmable output de-skew adjustments in steps as small as
16ps
Register programmable through I
2
C or via external I
2
C EEPROM
Bypass clock paths and Reference Output for system tests
Power supply modes:
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 72QFN, lead-free RoHs (6)
•
Typical Applications
•
•
•
•
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
Gigabit and Terabit IP switches / routers
Wireless base station baseband
Data communications
•
•
•
•
•
•
•
•
©2018 Integrated Device Technology, Inc.
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January 31, 2018
8T49N1012 Datasheet
8T49N1012 Block Diagram
REF_OUT
LOS
LOCK
PLL_BYP
OSCI
OSC
OSCO
1
1, 2,
4, x2
FracN Div A
Fractional
Feedback
PLL
FracN Div B
FracN Div C
FracN Div D
Q0
Q1
Q2
Q3
Q4
Q5
CLK
nCLK
0
CLK_SEL
FracN Div E
FracN Div F
FracN Div G
nRST
Reset
Logic
Q6
Q7
Q8
Q9
OTP
Status Registers
Control Registers
FracN Div H
IntN Div I
I
2
C Master
SCLK
SDATA
SA1
I
2
C SLAVE
IntN Div J
Q10
Q11
Serial EEPROM
Figure 1.
8T49N1012
Functional Block Diagram
OE[1:0]
©2018 Integrated Device Technology, Inc.
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January 31, 2018
8T49N1012 Datasheet
Pin Assignment for 72-pin, 10mm x 10mm VFQFN Package
CAP_REF
CLK_SEL
nRST
V
CCCS
nCLK
V
CCO4
V
CCO5
CAP
V
CCA
V
CCA
V
CCA
V
CCA
LOS
CLK
nQ4
nQ5
Q4
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
Q5
REF_OUT
V
CCA
OSCI
OSCO
LOCK
V
CCO10
Q11
nQ11
Q10
nQ10
nc
Rsvd
V
CCO8
Q9
nQ9
Q8
nQ8
Rsvd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54
53
52
51
50
PLL_BYP
nc
Q0
nQ0
V
CCO0
V
CCO1
Q1
nQ1
nc
Rsvd
nc
V
CCO2
Q2
nQ2
nc
V
CCO3
Q3
nQ3
8XXXXXX
49
48
47
46
45
44
43
42
41
40
39
38
37
nc
nQ7
nc
SCLK
V
CCO7
nQ6
V
CCO6
V
CCD
V
CC
V
EE
nc
nc
Q7
OE0
Q6
Figure 2. Pinout Drawing
©2018 Integrated Device Technology, Inc.
SDATA
3
OE1
SA1
January 31, 2018
8T49N1012 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
1
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Name
REF_OUT
V
CCA
OSCI
OSCO
LOCK
V
CCO10
Q11
nQ11
Q10
nQ10
nc
Rsvd
V
CCO8
Q9
nQ9
Q8
nQ8
Rsvd
SA1
V
CCD
SCLK
SDATA
V
EE
V
CC
nc
nc
V
CCO7
Q7
nQ7
nc
OE0
nc
Q6
nQ6
V
CCO6
OE1
nQ3
Q3
Output
Power
Input
Output
Output
Power
Output
Output
Output
Output
Unused
Reserved
Power
Output
Output
Output
Output
Reserved
Input
Power
I/O
I/O
Power
Power
Unused
Unused
Power
Output
Output
Unused
Input
Unused
Output
Output
Power
Input
Output
Output
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Type
Description
Single-ended REF output. 1.8V LVCMOS/LVTTL interface levels.
Core analog functions supply pin.
Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal.
Crystal Output. This pin should be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
PLL lock indicator. LVCMOS/LVTTL interface levels.
Output supply for Q10 and Q11 output clock pairs.
Output Clock 11. Refer to the Output Drivers section for more details.
Output Clock 11. Refer to the Output Drivers section for more details.
Output Clock 10. Refer to the Output Drivers section for more details.
Output Clock 10. Refer to the Output Drivers section for more details.
No internal connection.
Reserved - leave unconnected.
Output supply for Q8 and Q9 output clock pairs.
Output Clock 9. Refer to the Output Drivers section for more details.
Output Clock 9. Refer to the Output Drivers section for more details.
Output Clock 8. Refer to the Output Drivers section for more details.
Output Clock 8. Refer to the Output Drivers section for more details.
Reserved - leave unconnected.
I
2
C lower address bit A1.
Core Digital functions supply voltage.
I
2
C interface bi-directional Clock.
I
2
C interface bi-directional Data.
Negative supply voltage.
Core functions supply voltage.
No internal connection.
No internal connection.
Output supply for Q7 output clock pair.
Output Clock 7. Refer to the Output Drivers section for more details.
Output Clock 7. Refer to the Output Drivers section for more details.
No internal connect.
Output enable. LVCMOS/LVTTL interface levels.
No internal connection.
Output Clock 6. Refer to the Output Drivers section for more details.
Output Clock 6. Refer to the Output Drivers section for more details.
Output supply for Q6 output clock pair.
Output enable. LVCMOS/LVTTL interface levels.
Output Clock 3. Refer to the Output Drivers section for more details.
Output Clock 3. Refer to the Output Drivers section for more details.
©2018 Integrated Device Technology, Inc.
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January 31, 2018
8T49N1012 Datasheet
Table 1. Pin Descriptions
1
(Continued)
Number
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Name
V
CCO3
nc
nQ2
Q2
V
CCO2
nc
Rsvd
nc
nQ1
Q1
V
CCO1
V
CCO0
nQ0
Q0
nc
PLL_BYP
nQ5
Q5
V
CCO5
nRST
nQ4
Q4
V
CCO4
LOS
V
CCA
CAP_REF
CAP
V
CCA
V
CCA
V
CCA
V
CCCS
CLK_SEL
Power
Unused
Output
Output
Power
Unused
Reserved
Unused
Output
Output
Power
Power
Output
Output
Unused
Input
Output
Output
Power
Input
Output
Output
Power
Output
Power
Analog
Analog
Power
Power
Power
Power
Input
Pullup
Pullup
Pulldown
Pulldown
Type
Description
Output supply for Q3 output clock pair.
No internal connection.
Output Clock 2. Refer to the Output Drivers section for more details.
Output Clock 2. Refer to the Output Drivers section for more details.
Output supply for Q2 output clock pair.
No internal connection.
Reserved - leave unconnected.
No internal connection.
Output Clock 1. Refer to the Output Drivers section for more details.
Output Clock 1. Refer to the Output Drivers section for more details.
Output supply for Q1 output clock pair.
Output supply for Q0 output clock pair.
Output Clock 0. Refer to the Output Drivers section for more details.
Output Clock 0. Refer to the Output Drivers section for more details.
No internal connection.
Bypass Selection. Allow PLL references to bypass PLL and appear at Q[0:3].
LVTTL / LVCMOS interface levels.
Output Clock 5. Refer to the Output Drivers section for more details.
Output Clock 5. Refer to the Output Drivers section for more details.
Output supply for Q5 output clock pair.
Master Reset input. LVTTL / LVCMOS interface levels.
0 = All registers and state machines are reset to their default values
1 = Device runs normally
Output Clock 4. Refer to the Output Drivers section for more details.
Output Clock 4. Refer to the Output Drivers section for more details.
Output supply for Q4 output clock pair.
Loss of reference to PLL indicator. LVCMOS/LVTTL interface levels.
Core analog function supply voltage.
PLL External Capacitance reference.
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
Core analog function supply voltage.
Core analog function supply voltage.
Core analog function supply voltage.
Supply voltage for status and control signals: nRST, LOCK, LOS, PLL_BYP,
OE[1:0].
Clock select pin:
0: CLK, nCLK
1: XTAL (default)
©2018 Integrated Device Technology, Inc.
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January 31, 2018
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