74HC158
Quad 2-input multiplexer; inverting
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC158 is specified in compliance with JEDEC
standard no. 7A.
The 74HC158 is a quad 2-input multiplexer which select 4 bits of data from two sources
and are controlled by a common data select input (S). The four outputs present the
selected data in the inverted form. The enable input (E) is active LOW.
When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input
conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74HC158. The state of S determines the particular register from which the data
comes. It can also be used as a function generator.
The device is useful for implementing highly irregular logic by generating any four of the
16 different functions of two variables with one variable common.
The 74HC158 is the logic implementation of a 4-pole, 2-position switch, where the position
of the switch is determined by the logic levels applied to S.
The logic equations for the output are:
1Y = E.(1l1.S
+
1l0.S)
2Y = E.(2l1.S
+
2l0.S)
3Y = E.(3l1.S
+
3l0.S)
4Y = E.(4l1.S
+
4l0.S)
The 74HC158 is identical to the 74HC157 but has inverting outputs.
2. Features
s
s
s
s
Low-power dissipation
Inverting data path
Complies with JEDEC standard no. 7A
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
Philips Semiconductors
74HC158
Quad 2-input multiplexer; inverting
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol
t
PHL
, t
PLH
Parameter
propagation delay
nI0, nI1 to nY
E to nY
S to nY
C
I
C
PD
[1]
Conditions
C
L
= 15 pF;
V
CC
= 5 V
Min
Typ
Max
Unit
-
-
-
-
V
I
= GND to V
CC
[1]
12
14
14
3.5
40
-
-
-
-
-
ns
ns
ns
pF
pF
input capacitance
power dissipation capacitance
per multiplexer
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74HC158N
74HC158D
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP16
SO16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT38-4
SOT109-1
Type number
9397 750 13805
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
2 of 16
Philips Semiconductors
74HC158
Quad 2-input multiplexer; inverting
5. Functional diagram
3
5
6
11 10 14 13
2
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
1 S
MULTIPLEXER
15 E
OUTPUTS
1Y
4
2Y
7
3Y
9
4Y
12
001aab862
Fig 1. Functional diagram
1
1
2
3
5
6
11
10
14
13
15
S
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
E
001aab860
G1
EN
MUX
15
4
1Y
2
3
5
1
1
4
2Y
7
7
3Y
9
6
14
4Y
12
12
13
11
9
10
001aab861
Fig 2. Logic symbol
Fig 3. IEC logic symbol
9397 750 13805
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
3 of 16
Philips Semiconductors
74HC158
Quad 2-input multiplexer; inverting
S
E
1I0
1Y
1I1
2I0
2Y
2I1
3I0
3Y
3I1
4I0
4Y
4I1
001aab863
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
16 V
CC
15 E
14 4I0
13 4I1
158
5
6
7
8
001aab859
12 4Y
11 3I0
10 3I1
9
3Y
Fig 5. Pin configuration
9397 750 13805
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
4 of 16
Philips Semiconductors
74HC158
Quad 2-input multiplexer; inverting
6.2 Pin description
Table 3:
Symbol
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
3Y
3I1
3I0
4Y
4I1
4I0
E
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
common data select input
data input 1 from source 0
data input 1 from source 1
multiplexer output 1
data input 2 from source 0
data input 2 from source 1
multiplexer output 2
ground (0 V)
multiplexer output 3
data input 3 from source 1
data input 3 from source 0
multiplexer output 4
data input 4 from source 1
data input 4 from source 0
enable input (active LOW)
positive supply voltage
7. Functional description
7.1 Function table
Table 4:
Control
E
H
L
S
X
L
H
Function
[1]
Input
nI0
X
L
H
X
X
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Output
nl1
X
X
X
L
H
nY
H
H
L
H
L
9397 750 13805
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
5 of 16
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
