NJU3713A
12-BIT SERIAL TO PARALLEL CONVERTER
GENERAL DESCRIPTION
The
NJU3713A
is a 12-bit serial to parallel converter
especially applying to MPU outport expander. It can
operate from 2.4V to 5.5V.
The effective outport assignment of MPU is available
as the connection between
NJU3713A
and MPU using
only 4 lines.
The serial data synchronizing with 5MHz or more
clock can be input to the serial data input terminal and
the data are output from parallel output buffer through
serial in parallel out shift register and parallel data
latches.
The hysteresis input circuit realizes wide noise
margin and the high drive-ability output buffer (25mA)
can drive LED directly.
PACKAGE OUTLINE
NJU3713AV
FEATURES
12-Bit Serial In Parallel Out
Hysteresis Input
0.5V typ at 5V
Operating Voltage
2.4 to 5.5V
Maximum Operating Frequency 5MHz
Output Current
25mA at 5V, 5mA at 3V
C-MOS Technology
Package Outline
SSOP20
PIN CONFIGURATION
P5
P6
P7
P8
V
SS
NC
P9
P10
P11
P12
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
P4
P3
P2
P1
NC
CLR
STB
CLK
DATA
NJU3713AV
BLOCK DIAGRAM
DATA
Shift Register
Latch Circuit
CLK
P1
P2
P3
P11
P12
STB
CLR
Controller Circuit
Ver.2012-03-15
-1-
NJU3713A
TERMINAL DESCRIPTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
P5
P6
P7
P8
V
SS
NC
P9
P10
P11
P12
DATA
CLK
STB
CLR
NC
P1
P2
P3
P4
V
DD
I/O
O
O
O
O
-
-
O
O
O
O
I
I
I
I
-
O
O
O
O
-
FUNCTION
Parallel Conversion Data Output Terminals
GND
Non Connection
Parallel Conversion Data Output Terminals
Serial Data Input Terminal
Clock Signal Input Terminal
Strobe Signal Input Terminal
Clear Signal Input Terminal
Non Connection
Parallel Conversion Data Output Terminals
Power Supply Terminal (2.4 to 5.5V)
-2-
Ver.2012-03-15
NJU3713A
NJU3555
FUNCTIONAL DESCRIPTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Normally, the CLR terminal should be "H" level.
(2) Data Transmission
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
the clock signal should be controlled for data order.
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
to protect the noise.
CLK
X
STB
X
H
L
H
L
H
CLR
L
H
OPERATION
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
Note 1)
X: Don’t care
Ver.2012-03-15
-3-
NJU3713A
TIMING CHART
CLK
CLR
STB
DATA
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
-4-
Ver.2012-03-15
NJU3713A
NJU3555
ABSOLUTE MAXIMUM RATINGS
(Ta=25°C)
PARAMETER
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Output Current
Output Short Current
(P1~P12 Terminals)
(Note 5)
SYMBOL
V
DD
V
I
V
O
I
O
I
OSD
P
D
Topr
Tstg
RATINGS
-0.5 ~ +7.0
V
SS
-0.5 ~ V
DD
+0.5
V
SS
-0.5 ~ V
DD
+0.5
±25
V
O
=7V, V
I
=0V
V
O
=0V, V
I
=7V
20 (max)
-20 (max)
UNIT
V
V
V
mA
mA
mW
°C
°C
Power Dissipation
(Note 6)
675 (SSOP)
(Note6)
-25 ~ +85
-65 ~+150
Operating Temperature Range
Storage Temperature Range
Note 2)
All voltage are relative to V
SS
=0V reference.
Note 3)
Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also
Note 4)
Note 5)
Note 6)
recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause
malfunctions and impact on the reliability.
To stabilize the IC operation, place decoupling capacitor between V
DD
and V
SS
.
V
DD
=7V, V
SS
=0V, less than 1 second per pin.
EIA/JEDEC Standard Test Board (76.2 x 114.3 x 1.6mm, 2layers, FR-4) mounting.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Operating Current
High-level Input Voltage
Low-level Input Voltage
Input Leakage Current
SYMBOL
(V
DD
=2.4~5.5V, V
SS
=0V, Ta=25°C, unless otherwise noted)
CONDITION
MIN
TYP
MAX
UNIT
2.4
V
IH
=V
DD
, V
IL
=V
SS
-
0.7V
DD
V
SS
V
I
=0
~
V
DD
I
OH
=-25mA
V
DD
I
DDS
V
IH
V
IL
I
LI
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5
0.1
V
DD
0.3V
DD
10
V
DD
V
DD
V
DD
V
DD
1.5
0.8
0.4
0.5
V
mA
V
V
µA
-10
V
DD
-1.5
P1~P12
Terminals
High-level Output Voltage
(Note 7)
V
OHD
V
DD
=5V
I
OH
=-15mA
I
OH
=-10mA
V
DD
-1.0
V
DD
-0.5
V
DD
-0.5
V
SS
V
V
DD
=3V
I
OH
=-5mA
I
OL
=+25mA
Low-level Output Voltage
(Note 7)
V
OLD
V
DD
=5V
I
OL
=+15mA
I
OL
=+10mA
P1~P12
Terminals
V
SS
V
SS
V
SS
V
V
DD
=3V
operation should be required.
I
OL
=+5mA
Note 7)
Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating
Ver.2012-03-15
-5-
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