NXP Semiconductors
Data Sheet: Technical Data
K65P169CM180SF5V2
Rev. 4, 04/2017
Kinetis K65 Sub-Family
180 MHz ARM® Cortex®-M4F Microcontroller.
The K65 sub-family members provide greater performance,
memory options up to 2 MB total flash and 256 KB of SRAM, as
well as higher peripheral integration with features such as Dual
USB and a 10/100 Mbit/s Ethernet MAC. These devices maintain
hardware and software compatibility with the existing Kinetis
family. This product also offers:
• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run
mode
• Smarter peripherals with operation in Stop modes
MK65FN2M0CAC18R
MK65FX1M0CAC18R
169 WLCSP (AC)
5.6 mm x 5.5 mm Pitch 0.4 mm
Performance
Memories and memory expansion
• Up to 180 MHz ARM Cortex-M4 based core with DSP
• Up to 2 MB program flash memory on non-
instructions and Single Precision Floating Point unit
FlexMemory devices with 256 KB RAM
• Up to 1 MB program flash memory and 256 KB of
System and Clocks
FlexNVM on FlexMemory devices
• Multiple low-power modes to provide power
• 4 KB FlexRAM on FlexMemory devices
optimization based on application requirements
• FlexBus external bus interface and SDRAM controller
• Memory protection unit with multi-master protection
Analog modules
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• Two 16-bit SAR ADCs and two 12-bit DAC
• 48 MHz internal reference
• Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
Security
• Voltage reference 1.2V
• Hardware random-number generator
Communication interfaces
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
• Ethernet controller with MII and RMII interface to
external PHY and hardware IEEE 1588 capability
Timers
• USB high-/full-/low-speed On-the-Go with on-chip
• Four Periodic interrupt timers
high speed transceiver
• 16-bit low-power timer
• USB full-/low-speed OTG with on-chip transceiver
• Two 16-bit low-power timer PWM modules
• Two CAN, three SPI and four I2C modules
• Two 8-channel motor control/general purpose/PWM
• Low Power Universal Asynchronous Receiver/
timers
Transmitter 0 (LPUART0) and five standard UARTs
• Two 2-ch quad decoder/general purpose timers
• Secure Digital Host Controller (SDHC)
• Real-time clock
• I2S module
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
Operating Characteristics
• Voltage/Flash write voltage range:1.71 to 3.6 V
• Temperature range (ambient): -40 to 85°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
1
Part Number
Flash
MK65FN2M0CAC18R
MK65FX1M0CAC18R
2 MB
1.25 MB
Memory
SRAM
256KB
256KB
116
116
Maximum number of I\O's
1. To confirm current availability of orderable part numbers, go to
http://www.nxp.com
and perform a part number search.
Related Resources
Type
Selector
Guide
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
Resource
Solution Advisor
K65P169M180SF5RMV2
1
This document.
The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N
1
a particular device mask set.
Package dimensions are provided in package drawings.
WLCSP 169-pin:
98ASA00222D
1
1. To find the associated resource, go to
http://www.nxp.com
and perform a search using this term.
2
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Kinetis K65 Sub-Family
ARM
®
Cortex
®
-M4
Core
System
Internal
and external
watchdogs
Debug
interfaces
Interrupt
controller
DSP
Memory
protection
Memories and Memory Interfaces
Program
flash
Clocks
Phase-
locked loop
Frequency-
locked loop
Low/high
frequency
oscillators
RAM
FlexMemory
Serial
programming
interface
SDRAM
controller
Cache
Floating-
point unit
DMA
External
bus
Low-leakage
wakeup
Internal
reference
clocks
and Integrity
CRC
Random
number
generator
Hardware
encryption
Security
Analog
16-bit ADC
x2
Timers
Timers
x4 (20ch)
Communication Interfaces
I
C
x4
UART
x5
SPI
x3
CAN
x2
IEEE 1588
Ethernet
2
Human-Machine
Interface (HMI)
GPIO
Xtrinsic
touch-sensing
interface
I
S
x1
Secure
Digital
USB LS/FS
OTG
controller
with
transceiver
2
Analog
comparator
x4
6-bit DAC
x4
12-bit DAC
x2
Carrier
modulator
transmitter
Programmable
delay block
Periodic
interrupt
timers
Low power
timer
Voltage
reference
Independent
real-time
clock
IEEE 1588
Timers
LPUART
USB LS/FS/HS
OTG
controller
with
transceiver
USB DCD/
USBHSDCD
USB voltage
regulator
Low power
TPM x 2 (4ch)
Figure 1. K65 Block Diagram
Kinetis K65 Sub-Family, Rev. 4, 04/2017
3
NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1
Voltage and current operating requirements.....7
2.2.2
LVD and POR operating requirements............. 8
2.2.3
Voltage and current operating behaviors.......... 9
2.2.4
Power mode transition operating behaviors......10
2.2.5
Power consumption operating behaviors.......... 12
2.2.6
EMC radiated emissions operating behaviors...16
2.2.7
Designing with radiated emissions in mind....... 17
2.2.8
Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1
Device clock specifications............................... 17
2.3.2
General switching specifications....................... 18
2.4 Thermal specifications..................................................... 19
2.4.1
Thermal operating requirements....................... 19
2.4.2
Thermal attributes............................................. 19
3 Peripheral operating requirements and behaviors.................. 20
3.1 Core modules.................................................................. 21
3.1.1
Debug trace timing specifications..................... 21
3.1.2
JTAG electricals................................................ 21
3.2 System modules.............................................................. 24
3.3 Clock modules................................................................. 24
3.3.1
MCG specifications........................................... 24
3.3.2
IRC48M specifications...................................... 27
3.3.3
Oscillator electrical specifications..................... 28
3.3.4
32 kHz oscillator electrical characteristics.........31
3.4 Memories and memory interfaces................................... 31
3.4.1
Flash (FTFE) electrical specifications............... 31
3.4.2
EzPort switching specifications......................... 36
3.4.3
Flexbus switching specifications....................... 37
3.4.4
SDRAM controller specifications.......................40
3.5 Security and integrity modules........................................ 43
3.6 Analog............................................................................. 43
3.6.1
ADC electrical specifications.............................43
3.6.2
CMP and 6-bit DAC electrical specifications.....48
3.6.3
12-bit DAC electrical characteristics................. 50
3.6.4
Voltage reference electrical specifications........ 53
3.7 Timers..............................................................................54
3.8 Communication interfaces............................................... 54
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
Ethernet switching specifications...................... 55
USB Voltage Regulator Electrical
Specifications.................................................... 58
USB Full Speed Transceiver and High Speed
PHY specifications............................................ 59
USB DCD electrical specifications.................... 60
CAN switching specifications............................ 60
DSPI switching specifications (limited voltage
range)................................................................60
DSPI switching specifications (full voltage
range)................................................................62
3.8.8
Inter-Integrated Circuit Interface (I2C) timing....64
3.8.9
UART switching specifications.......................... 65
3.8.10 Low Power UART switching specifications....... 65
3.8.11 SDHC specifications......................................... 66
3.8.12 I2S switching specifications.............................. 67
3.9 Human-machine interfaces (HMI)....................................73
3.9.1
TSI electrical specifications...............................73
4 Dimensions............................................................................. 73
4.1 Obtaining package dimensions....................................... 73
5 Pinout...................................................................................... 74
5.1 K65_169WLCSP Signal Multiplexing and Pin
Assignments.................................................................... 74
5.2 Recommended connection for unused analog and
digital pins........................................................................81
5.3 K65 Pinouts..................................................................... 83
6 Ordering parts......................................................................... 84
6.1 Determining valid orderable parts....................................84
7 Part identification.....................................................................85
7.1 Description.......................................................................85
7.2 Format............................................................................. 85
7.3 Fields............................................................................... 85
7.4 Example...........................................................................86
8 Terminology and guidelines.................................................... 86
8.1 Definitions........................................................................ 86
8.2 Examples......................................................................... 87
8.3 Typical-value conditions.................................................. 87
8.4 Relationship between ratings and operating
requirements....................................................................88
8.5 Guidelines for ratings and operating requirements..........88
9 Revision History...................................................................... 88
4
NXP Semiconductors
Kinetis K65 Sub-Family, Rev. 4, 04/2017
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
T
STG
T
SDR
Description
Storage temperature
Solder temperature, lead-free
Min.
–55
—
Max.
150
260
Unit
°C
°C
Notes
1
2
1. Determined according to JEDEC Standard JESD22-A103,
High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
—
Max.
1
Unit
—
Notes
1
1. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
V
HBM
V
CDM
I
LAT
Description
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device
model
Latch-up current at ambient temperature of 105°C
Min.
-2000
-500
-100
Max.
+2000
+500
+100
Unit
V
V
mA
Notes
1
2
3
1. Determined according to JEDEC Standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101,
Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78,
IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K65 Sub-Family, Rev. 4, 04/2017
5
NXP Semiconductors
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