• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
32 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
–
ECRC support
–
AER on all ports
–
SECDED ECC protection on all internal RAMs
–
End-to-end data path parity protection
–
Checksum Serial EEPROM content protected
–
Autonomous link reliability (preserves system operation in the
presence of faulty links)
–
Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Test and Debug
–
On-chip link activity and status outputs available for Port 0
(upstream port)
–
Per port link activity and status outputs available using
external I
2
C I/O expander for all other ports
–
SerDes test modes
–
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Power Supplies
–
Requires only two power supply voltages (1.0 V and 2.5 V)
Note that a 3.3V is preferred for V
DD
I/O
–
No power sequencing requirements
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with
1mm ball spacing
–
Compatible with IDT 89HPES34H16 PCIe Gen1 switch
Note:
For pin compatibility issues, contact the IDT help desk
at
ssdhelp@idt.com.
Product Description
Utilizing standard PCI Express interconnect, the PES34H16G2
provides the most efficient I/O connectivity for applications requiring
high throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 34 GBps (272 Gbps) of aggregated,
full-duplex switching capacity through 34 integrated serial lanes, using
proven and robust IDT technology. Each lane provides 5 GT/s of band-
width in both directions and is fully compliant with PCI Express Base
Specification, Revision 2.0.
The PES34H16G2 is based on a flexible and efficient layered archi-
tecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers. The PES34H16G2 can operate either as a store
and forward switch or a cut-through switch. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to enable efficient switching and I/O connectivity.
The PES34H16G2 is a
partitionable
PCIe switch. This means that in
addition to operating as a standard PCI express switch, the
PES34H16G2 ports may be partitioned into groups that logically
operate as completely independent PCIe switches. Figure 2 illustrates a
three partition PES34H16G2 configuration.
2 of 54
November 28, 2011
IDT 89HPES34H16G2 Data Sheet
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Port
Arbitration
16-Port Switch Core
Frame Buffer
Scheduler
DL/Transaction Layer
DL/Transaction Layer
SerDes
. . . .
34 PCI Express Lanes
Up to 6 x4 ports and 10 x1 Ports
Figure 1 PES34H16G2 Block Diagram
(10)
SerDes
x1
x1
Partition 1
Upstream Port
Partition 2
Upstream Port
Partition 3
Upstream Port
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1 – Virtual PCI Bus
Partition 2 – Virtual PCI Bus
Partition 3 – Virtual PCI Bus
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1
Downstream Ports
Partition 2
Downstream Ports
Partition 3
Downstream Ports
Figure 2 Example of Usage of Switch Partitioning
3 of 54
November 28, 2011
IDT 89HPES34H16G2 Data Sheet
SMBus Interface
The PES34H16G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES34H16G2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES34H16G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is
also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
Bit
1
2
3
4
5
6
7
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 3 Split SMBus Interface Configuration
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
4 of 54
November 28, 2011
IDT 89HPES34H16G2 Data Sheet
Hot-Plug Interface
The PES34H16G2 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the
device, the PES34H16G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface.
Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES34H16G2 generates an SMBus transaction
to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is
received on the IOEXPINTN input pin (alternate function of GPIO) of the PES34H16G2. In response to an I/O expander interrupt, the PES34H16G2
generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES34H16G2 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES34H16G2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Signal
PE00RN[3:0]
PE00RP[3:0]
PE00TN[3:0]
PE00TP[3:0]
PE01RN[3:0]
PE01RP[3:0]
PE01TN[3:0]
PE01TP[3:0]
PE02RN[3:0]
PE02RP[3:0]
PE02TN[3:0]
PE02TP[3:0]
PE03RN[3:0]
PE03RP[3:0]
PE03TN[3:0]
PE03TP[3:0]
PE04RN[3:0]
PE04RP[3:0]
PE04TN[3:0]
PE04TP[3:0]
PE05RN[3:0]
PE05RP[3:0]
Type
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive pairs for
port 0.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 0.
PCI Express Port 1 Serial Data Receive.
Differential PCI Express receive pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs
for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs
for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive pairs for
port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive pairs for
port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs
for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs
for lanes 4 through 7.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive pairs for
port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express transmit pairs for
port 4.
PCI Express Port 5 Serial Data Receive.
Differential PCI Express receive pairs for
port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs
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