AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Features
•
Fast access time from clock: 5.4/5.4 ns
•
Fast clock rate: 166/143 MHz
•
Fully synchronous operation
•
Internal pipelined architecture
•
Four internal banks (1M x 32-bit x 4bank)
•
Programmable Mode
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & Interleaved
- Burst-Read-Single-Write
•
Burst stop function
•
Individual byte controlled by DQM0-3
•
Auto Refresh and Self Refresh
•
4096 refresh cycles/64ms
•
Single 3.3V ±0.3V power supply
•
Operating Temperature
- Commercial (0°C~+70°C)
- Industrial (-40°C~+85°C)
•
Interface: LVTTL
•
Package:
- 86-pin 400 mil plastic TSOP II package (Pb free and Halogen free)
Overview
The 128Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 134,217,728 Mbits. It
is internally configured as a quad 1M x 32 DRAM
with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Each of the 1M x 32 bit banks is organized as
4096 rows by 256 columns by 32 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth.
Table
1.
Ordering Information
Product part No
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Org
4M
x 32
4M
x 32
4M
x 32
Temperature
Industrial
-40°C
to
+85°C
Commercial
0°C to
+70°C
Commercial
0°C to
+70°C
Max Clock (MHz)
166 MHz
166 MHz
143 MHz
Package
86-pin TSOP II
86-pin TSOP II
86-pin TSOP II
Confidential
-2/47-
Rev.1.0
Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Pin Descriptions
Symbol
CLK
Type
Input
Description
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock(set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When all banks are in the
idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until exiting the same
mode. The input buffers, including CLK, are disabled during Power Down and Self
Refresh modes, providing low standby power.
Bank Activate:
BA0 and BA1 defines to which bank the BankActivate, Read, Write,
or BankPrecharge command is being applied. The bank address BA0 and BA1 is
used latched in mode register set.
Address Inputs:
A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 1M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the op-
code during a Mode Register Set or Special Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS# "LOW." Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH."
Write Enable:
The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
Data Input/Output Mask: Data Input Mask:
DQM0-DQM3 are byte specific. Input
data is masked when DQM is sampled HIGH during a write cycle. DQM3 masks
DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0.
Data I/O:
The DQ0-31 input and output data are synchronized with the positive
edges of CLK. The I/Os are byte-maskable during Reads and Writes.
-5/47-
Rev.1.0
Sep.2015
Table
2.
Pin Details
CKE
Input
BA0, BA1
Input
A0-A11
Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
DQM0-
DQM3
Input
DQ0-
DQ31
Confidential
Input/
Output
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