MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
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The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low (HC125A) or active−high (HC126A).
Features
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
OE1
A1
Y1
OE2
A2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
OE4
A4
Y4
OE3
A3
Y3
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7 A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
HC125A
Active−Low Output Enables
A1
OE1
A2
OE2
A3
OE3
A4
OE4
2
1
5
4
9
10
12
13
11
Y4
8
Y3
6
Y2
3
Y1
MARKING DIAGRAMS
14
HC12xAG
AWLYWW
1
SOIC−14 NB
x
A
L, WL
Y, YY
W, WW
G or
G
1
TSSOP−14
14
HC
12xA
ALYWG
G
HC126A
Active−High Output Enables
A1
OE1
A2
OE2
A3
OE3
A4
OE4
2
1
5
4
9
10
12
13
11
Y4
8
Y3
A
H
L
X
6
Y2
3
Y1
= 5, 6
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
HC125A
Inputs
OE
L
L
H
Output
Y
H
L
Z
A
H
L
X
HC126A
Inputs
OE
H
H
L
Output
Y
H
L
Z
ORDERING INFORMATION
PIN 14 = V
CC
PIN 7 = GND
©
Semiconductor Components Industries, LLC, 2014
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
1
August, 2014 − Rev. 15
Publication Order Number:
MC74HC125A/D
MC74HC125A, MC74HC126A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
Value
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±35
±75
500
450
–65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
0
–55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HC125A, MC74HC126A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
6.0
6.0
–55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply Current
(per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
−
–55 to
25_C
90
36
18
15
120
45
24
20
90
36
18
15
60
22
12
10
10
15
v
85_C
115
45
23
20
150
60
30
26
115
45
23
20
75
28
15
13
10
15
v
125_C
135
60
27
23
180
80
36
31
135
60
27
23
90
34
18
15
10
15
Unit
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
ns
C
in
C
out
Maximum Input Capacitance
Maximum 3−State Output Capacitance (Output in High−Impedance State)
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
2
f
30
+ I
CC
V
CC
.
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
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3
MC74HC125A, MC74HC126A
SWITCHING WAVEFORMS
V
CC
50%
GND
V
CC
GND
t
PHL
90%
50%
10%
t
TLH
t
THL
OUTPUT Y
OE (HC126A)
50%
GND
t
PZL
OUTPUT Y
50%
t
PZH
50%
t
PHZ
90%
t
PLZ
10%
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
V
CC
OE (HC125A)
t
r
INPUT A
t
PLH
OUTPUT Y
90%
50%
10%
t
f
Figure 1.
Figure 2.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL.
CONNECT TO GND WHEN
TESTING t
PHZ
and t
PZH.
C
L
*
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
V
CC
OE
A
Y
HC125A
(1/4 OF THE DEVICE)
V
CC
OE
A
Y
HC126A
(1/4 OF THE DEVICE)
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4
MC74HC125A, MC74HC126A
ORDERING INFORMATION
Device
MC74HC125ADG
MC74HC125ADR2G
MC74HC125ADTG
MC74HC125ADTR2G
MC74HC126ADG
MC74HC126ADR2G
MC74HC126ADTR2G
NLV74HC125ADG*
NLV74HC125ADR2G*
NLV74HC125ADTG*
NLV74HC125ADTR2G*
NLV74HC126ADR2G*
NLV74HC126ADTR2G*
Package
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
Shipping
†
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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