74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 5 — 29 January 2016
Product data sheet
1. General description
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time to guarantee predictable behavior. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added
for each stage that is added. The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input will disable the parallel load gates, override both clock inputs
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC193: CMOS level
For 74HCT193: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
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Product data sheet
Rev. 5 — 29 January 2016
3 of 28
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
Nexperia
Presettable synchronous 4-bit binary up/down counter
74HC193; 74HCT193
Fig 4.
Logic diagram
.
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16
Fig 6.
Pin configuration TSSOP16 and SSOP16
5.2 Pin description
Table 2.
Symbol
D0
D1
D2
D3
Q0
Q1
Q2
Q3
CPD
CPU
GND
PL
TCU
TCD
MR
V
CC
[1]
Pin description
Pin
15
1
10
9
3
2
6
7
4
5
8
11
12
13
14
16
Description
data input 0
data input 1
data input 2
data input 3
flip-flop output 0
flip-flop output 1
flip-flop output 2
flip-flop output 3
count down clock input
[1]
count up clock input
[1]
ground (0 V)
asynchronous parallel load input (active LOW)
terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)
asynchronous master reset input (active HIGH)
supply voltage
LOW-to-HIGH, edge triggered.
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 5 — 29 January 2016
©
4 of 28
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
6. Functional description
Table 3.
Function table
[1]
Inputs
MR
Reset (clear)
Parallel load
H
H
L
L
L
L
Count up
Count down
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH clock transition.
[2]
[3]
TCU = CPU at terminal count up (HHHH)
TCD = CPD at terminal count down (LLLL).
Operating mode
Outputs
CPU CPD D0
X
X
X
X
L
H
H
L
H
L
H
X
X
H
X
X
L
L
H
H
X
X
D1
X
X
L
L
H
H
X
X
D2
X
X
L
L
H
H
X
X
D3
X
X
L
L
H
H
X
X
Q0
L
L
L
L
H
H
Q1
L
L
L
L
H
H
Q2
L
L
L
L
H
H
Q3
L
L
L
L
H
H
TCU TCD
H
H
H
H
L
H
H
[2]
H
L
H
L
H
H
H
H
H
[3]
PL
X
X
L
L
L
L
H
H
L
L
count up
count down
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 5 — 29 January 2016
©
5 of 28
Nexperia B.V. 2017. All rights reserved
微控制器 MCU
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