2:1 Differential-to-LVPECL Multiplexer
Datasheet
853S01
General Description
The 853S01 is a high performance 2:1 Differential-to-LVPECL
Multiplexer. The 853S01 can also perform differential translation
because the differential inputs accept LVPECL, LVDS and CML
levels. The 853S01 is packaged in a small 3mm x 3mm 16 VFQFN
package, making it ideal for use on space constrained boards.
Features
•
•
•
•
•
•
•
•
•
One LVPECL output pair
Two selectable differential LVPECL clock inputs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML
Translates LVCMOS/LVTTL input signals to LVPECL levels by
using a resistor bias network on nPCLKx, nPCLKx
Part-to-part skew: 150ps (maximum)
Propagation delay: 490ps (maximum)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
CLK_SEL
Pulldown
V
BB
1
0
Q
nQ
Pin Assignments
PCLK0 1
nPCLK0
2
16 15 14 13
12 V
EE
11 Q
10 nQ
9 V
EE
5
V
BB
V
EE
V
CC
V
EE
nc
PCLK1 3
nPCLK1 4
6
CLK_SEL
7
nc
8
V
CC
ICS853S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
CLK_SEL
nc
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
V
EE
V
EE
V
CC
V
EE
Q
nQ
V
EE
853S01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925
mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision B, March 4, 2016
853S01 Datasheet
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 16
8, 13
9, 12, 14, 15
10, 11
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
BB
CLK_SEL
nc
V
CC
V
EE
nQ, Q
Input
Input
Input
Input
Output
Input
Unused
Power
Power
Output
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS/LVTTL interface levels.
No connect.
Positive supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
37
Maximum
Units
pF
k
k
Function Tables
Table 3. Control Input Function Table
CLK_SEL
0
1
Input Selected
PCLK0, nPCLK0
PCLK1, nPCLK1
©2016 Integrated Device Technology, Inc.
2
Revision B, March 4, 2016
853S01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink/Source, I
BB
Package Thermal Impedance,
JA
16 VFQFN
16 TSSOP
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±0.5mA
74.7C/W (0 mps)
100C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
26
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
24
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V±5% or 2.5V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
Input High
Current
Input Low
Current
V
CC
= 3.3V
V
CC
= 2.5V
CLK_SEL
CLK_SEL
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
©2016 Integrated Device Technology, Inc.
3
Revision B, March 4, 2016
853S01 Datasheet
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
V
BB
Parameter
Input High Current
PCLK0, PCLK1,
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Output High Voltage;
NOTE 3
Output Low Voltage;
NOTE 3
Peak-to-Peak Output Voltage Swing
Bias Voltage
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-10
-150
150
1.2
V
CC
– 1.125
V
CC
– 1.895
0.495
1.695
1200
V
CC
V
CC
– 0.875
V
CC
– 1.62
0.975
2.145
Minimum
Typical
Maximum
150
Units
µA
µA
µA
mV
V
V
V
V
V
NOTE 1: V
IL
should not be less than V
EE
– 0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
to V
CC
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= 2.5V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
V
BB
Parameter
Input High Current
PCLK0, PCLK1,
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input Voltage; NOTE
1, 2
Output High Voltage;
NOTE 3
Output Low Voltage;
NOTE 3
Peak-to-Peak Output Voltage Swing
Bias Voltage
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
-10
-150
150
1.2
V
CC
– 1.125
V
CC
– 1.895
0.495
0.935
1200
V
CC
V
CC
– 0.875
V
CC
– 1.62
0.975
1.305
Minimum
Typical
Maximum
150
Units
µA
µA
µA
mV
V
V
V
V
V
NOTE 1: V
IL
should not be less than V
EE
– 0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
to V
CC
– 2V.
©2016 Integrated Device Technology, Inc.
4
Revision B, March 4, 2016
853S01 Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
CC
= 3.3V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
MUX
ISOL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Input Skew
Part-to-Part Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS,
refer to Additive Phase Jitter
section; NOTE 4
Output Rise/ Fall Time
MUX Isolation; NOTE 5
622MHz, Integration Range:
12kHz - 20MHz
20% to 80%
ƒ
OUT
½
622MHz
100
81
0.024
240
240
Test Conditions
Minimum
Typical
Maximum
2.5
490
40
150
Units
GHz
ps
ps
ps
ps
ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ
1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 4: Driving only one input clock.
NOTE 5: Q, nQ output measured differentially. See
Parameter Measurement Information
for MUX Isolation diagram
Table 5B. AC Characteristics,
V
CC
= 2.5V±5%; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tsk(i)
tsk(pp)
tjit
t
R
/ t
F
MUX
ISOL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Input Skew
Part-to-Part Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS,
refer to Additive Phase Jitter
section; NOTE 4
Output Rise/ Fall Time
MUX Isolation; NOTE 5
622MHz, Integration Range:
12kHz - 20MHz
20% to 80%
ƒ
OUT
½
622MHz
100
81
0.024
240
240
Test Conditions
Minimum
Typical
Maximum
2.5
490
40
150
Units
GHz
ps
ps
ps
ps
ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ
1.0GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential
cross points.
NOTE 4: Driving only one input clock.
NOTE 5: Q, nQ output measured differentially. See
Parameter Measurement Information
for MUX Isolation diagram
©2016 Integrated Device Technology, Inc.
5
Revision B, March 4, 2016
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