www.fairchildsemi.com
FAN4810
Power Factor Correction Controller
Features
• TriFault Detect™ for UL1950 compliance and enhanced
safety
• Slew rate enhanced transconductance error amplifier for
ultra-fast PFC response
• Low power: 200µA startup current, 5.5mA operating
current
• Low total harmonic distortion, high PF
• Average current, continuous boost leading edge PFC
• Current fed gain modulator for improved noise immunity
• Overvoltage and brown-out protection, UVLO, and soft
start
• Synchronized clock output
General Description
The FAN4810 is a controller for power factor corrected,
switched mode power supplies. The FAN4810 includes
circuits for the implementation of leading edge, average
current, “boost” type power factor correction and results in a
power supply that fully complies with IEC1000-3-2 specifi-
cation. It also includes a TriFault Detect™ function to help
ensure that no unsafe conditions will result from single
component failure in the PFC. Gate-driver with 1A
capability minimizes the need for external driver circuit.
Low power requirements improve efficiency and reduce
component costs. The PFC also includes peak current
limiting, input voltage brownout protection and a over-
voltage comparator shuts down the PFC section in the event
of a sudden decrease in load. The clock-out signal can be
used to synchronize down-stream PWM stages in order to
reduce system noise.
Block Diagram
16
VEAO
VFB
15
2.5V
IAC
2
VRMS
4
ISENSE
3
RAMP 1
7
OSCILLATOR
R
Q
GAIN
MODULATOR
3.6kΩ
VEA
–
+
1
IEAO
POWER FACTOR CORRECTOR
0.5V
3.6kΩ
IEA
+
-
13
VCC
OVP
+
2.75V
–
TRI-FAULT
+
–
VCC
17V
7.5V
REFERENCE
S
Q
VREF
14
+
–
-1V
+
–
R
S
Q
PFC OUT
Q
12
PFC ILIMIT
8
DUTY CYCLE
LIMIT
6
1.25V
VCC
25µA
+
–
CLKOUT
S
VFB
2.45V
–
+
Q
VIN OK
R
Q
11
5
CLKSD
9
VREF
10
VCC
UVLO
REV. 1.0.12 9/24/03
FAN4810
PRODUCT SPECIFICATION
Pin Configuration
FAN4810
(Pin Out)
IEAO 1
IAC 2
ISENSE 3
VRMS 4
CLKSD 5
NC 6
RAMP 1 7
NC 8
16 VEAO
15 VFB
14 VREF
13 VCC
12 PFC OUT
11 CLK OUT
10 GND
9
GND
TOP VIEW
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
IEAO
I
AC
I
SENSE
V
RMS
CLKSD
NC
RAMP 1
NC
GND
GND
CLK OUT
PFC OUT
V
CC
V
REF
V
FB
VEAO
Ground
Ground
Clock signal synchronized to PFC frequency
PFC driver output
Positive supply
Buffered output for the internal 7.5V reference
PFC transconductance voltage error amplifier input
PFC transconductance voltage error amplifier output
Oscillator timing node; timing set by R
T
C
T
Function
Slew rate enhanced PFC transconductance error amplifier output
PFC AC line reference input to Gain Modulator
Current sense input to the PFC Gain Modulator
PFC Gain Modulator RMS line voltage compensation input
Turn on/off PWM clock without disturbing PFC out
2
REV. 1.0.12 9/24/03
PRODUCT SPECIFICATION
FAN4810
Abolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
V
CC
I
SENSE
Voltage
Voltage on Any Other Pin
I
REF
I
AC
Input Current
Peak PFC OUT Current, Source or Sink
PFC OUT, CLK OUT Energy Per Cycle
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance (
θ
JA)
Plastic DIP
Plastic SOIC
-65
-5
GND - 0.3
Min.
Max.
18
0.7
V
CCZ
+ 0.3
10
10
1
1.5
150
150
260
80
105
Units
V
V
V
mA
mA
A
µJ
°C
°C
°C
°C/W
°C/W
Operating Conditions
Min.
Temperature Range
0
Max.
70
Units
°C
Electrical Characteristics
Unless otherwise specified, V
CC
= 15V, R
T
= 52.3k
Ω
, C
T
= 470pF, T
A
= Operating Temperature Range (Note 1)
Symbol
Parameter
Input Voltage Range
Transconductance
Feedback Reference Voltage
Input Bias Current
Output High Voltage
Output Low Voltage
Source Current
Sink Current
Open Loop Gain
Power Supply Rejection Ratio
Current Error Amplifier
Input Voltage Range
Transconductance
Input Offset Voltage
Input Bias Current
V
NON INV
= V
INV
, VEAO = 3.75V
-1.5
50
0
100
4
-0.5
2
150
15
-1.0
V
µ
mV
µA
11V < V
CC
< 16.5V
V
IN
= ±0.5V, V
OUT
= 6V
V
IN
= ±0.5V, V
OUT
= 1.5V
-40
40
50
50
Note 2
6.0
V
NON INV
= V
INV
, VEAO = 3.75V
Conditions
Min.
0
30
2.43
65
2.5
-0.5
6.7
0.1
-140
140
60
60
0.4
Typ.
Max. Units
5
90
2.57
-1.0
V
µ
V
µA
V
V
µA
µA
dB
dB
Voltage Error Amplifier
REV. 1.0.12 9/24/03
3
FAN4810
PRODUCT SPECIFICATION
Electrical Characteristics(Continued)
Unless otherwise specified, V
CC
= 15V, R
T
= 52.3k
Ω
, C
T
= 470pF, T
A
= Operating Temperature Range (Note 1)
Symbol
Parameter
Output High Voltage
Output Low Voltage
Source Current
Sink Current
Open Loop Gain
Power Supply Rejection Ratio
OVP Comparator
Threshold Voltage
Hysteresis
Tri-Fault Detect
Fault Detect HIGH
Time to Fault Detect HIGH
V
FB
= V
FAULT DETECT LOW
to
V
FB
= OPEN. 470pF from V
FB
to
GND
0.4
-0.9
120
2.65
2.75
2
2.85
4
V
ms
2.65
175
2.75
250
2.85
325
V
mV
11V < V
CC
< 16.5V
V
IN
= ±0.5V, V
OUT
= 6V
V
IN
= ±0.5V, V
OUT
= 1.5V
-40
40
60
60
Conditions
Min.
6.0
Typ.
6.7
0.65
-104
160
70
75
1.0
Max. Units
V
V
µA
µA
dB
dB
Fault Detect LOW
PFC I
LIMIT
Comparator
Threshold Voltage
(PFC I
LIMIT
V
TH
- Gain
Modulator Output)
Delay to Output
GAIN Modulator
Gain (Note 3)
I
AC
= 100µA, V
RMS
= V
FB
= 0V
I
AC
= 50µA, V
RMS
= 1.2V, V
FB
= 0V
I
AC
= 50µA, V
RMS
= 1.8V, V
FB
= 0V
I
AC
= 100µA, V
RMS
= 3.3V, V
FB
= 0V
Bandwidth
Output Voltage
Oscillator
Initial Accuracy
Voltage Stability
Temperature Stability
Total Variation
Ramp Valley to Peak Voltage
PFC Dead Time
C
T
Discharge Current
Reference
Output Voltage
Line Regulation
Load Regulation
T
A
= 25°C, I(V
REF
) = 1mA
11V <V
CC
<16.5V
0mA <I(V
REF
) < 10mA;
T
A
= 0°C to 70°C
V
RAMP 2
= 0V, V
RAMP 1
= 2.5V
Line, Temp
T
A
= 25°C
11V < V
CC
< 16.5V
I
AC
= 100µA
I
AC
= 350µA, V
RMS
= 1V, V
FB
= 0V
0.5
-1.0
220
150
0.6
-1.1
V
V
mV
300
1.05
2.40
1.25
0.40
ns
0.60
1.8
0.85
0.20
0.60
71
0.80
2.0
1.0
0.30
10
0.75
76
1
2
MHz
0.9
81
V
kHz
%
%
84
kHz
V
650
ns
mA
V
mV
mV
7.5
7.6
25
20
68
2.5
350
3.5
7.4
5.5
7.5
10
10
4
REV. 1.0.12 9/24/03
PRODUCT SPECIFICATION
FAN4810
Electrical Characteristics(Continued)
Unless otherwise specified, V
CC
= 15V, R
T
= 52.3kΩ, C
T
= 470pF, T
A
= Operating Temperature Range (Note 1)
Symbol
Parameter
Temperature Stability
Total Variation
Long Term Stability
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
V
IEAO
> 4.0V
V
IEAO
< 1.2V
I
OUT
= -20mA
I
OUT
= -100mA
I
OUT
= 10mA, V
CC
= 9V
Output High Voltage
Rise/Fall Time
Clock
Duty Cycle
Supply
Start-up Current
Operating Current
Undervoltage Lockout
Threshold
Undervoltage Lockout
Hysteresis
V
CC
= 12V, C
L
= 0
14V, C
L
= 0
12.4
2.5
200
5.5
13
2.8
350
7
13.6
3.1
µA
mA
V
V
45
47
50
%
I
OUT
= 20mA
I
OUT
= 100mA
C
L
= 1000pF
V
CC
- 0.8V
V
CC
- 2V
50
90
95
0.4
0.7
0.4
0.8
2.0
0.8
0
%
%
V
V
V
V
V
ns
Line, Load, Temp
T
J
= 125°C, 1000 Hours
7.35
5
Conditions
Min.
Typ.
0.4
7.65
25
Max. Units
%
V
mV
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Includes all bias currents to other circuits connected to the V
FB
pin.
3. Gain = K x 5.3V; K = (I
GAINMOD
- I
OFFSET
) x [I
AC
(VEAO - 0.625)]
-1
; VEAO
MAX
=5V.
REV. 1.0.12 9/24/03
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
