CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
W option, wiper counter = 00h
U option, wiper counter = 00h
MIN
TYP
(NOTE 1)
10
50
-20
70
10/10/25
Voltage at pin from GND to V
CC
0.1
1
+20
200
MAX
UNIT
k
k
%
pF
µA
PARAMETER
R
H
to R
W
resistance
R
H
to R
W
resistance tolerance
R
W
C
H
/C
L
/C
W
I
LkgDCP
Wiper resistance
Potentiometer capacitance (Note 15)
Leakage on DCP pins (Note 15)
Wiper counter = 00h
V
CC
= 3.3V @ 25°C, wiper current =
V
CC
/R
TOTAL
RESISTOR MODE
(Measurements between R
W
i and R
H
i, i = 0, 1, 2 or 3)
RINL
(Note 5)
RDNL
(Note 4)
Roffset
(Note 3)
Integral non-linearity
Differential non-linearity
Offset
U option
W option
R
MATCH
(Note 6)
TC
R
(Note 7)
DCP to DCP matching
Resistance temperature coefficient
Any two DCPs at the same tap position with
the same terminal voltages
DCP register set between 20 hex and FF hex
DCP register set between 20 hex and FF
hex; monotonic over all tap positions
-1
-0.5
0
0
-2
±45
1
0.5
1
0.5
7
2
2
MI
(Note 2)
MI
(Note 2)
MI
(Note 2)
MI
(Note 2)
MI
(Note 2)
ppm/°C
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
I
CC1
I
SB
PARAMETER
V
CC
supply current (volatile write/
read)
V
CC
current (standby)
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read and write states)
V
CC
= +5.5V, I
2
C interface in standby state
V
CC
= +3.6V, I
2
C interface in standby state
I
LkgDig
Leakage current, at pins A0, A1, SDA, Voltage at pin from GND to V
CC
and SCL
-10
MIN
TYP
(NOTE 1)
MAX
1
5
2
10
UNIT
mA
µA
µA
µA
FN8096 Rev 1.00
January 16, 2006
Page 3 of 10
ISL90842
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
t
DCP
(Note 8)
PARAMETER
DCP wiper response time
TEST CONDITIONS
SCL falling edge of last bit of DCP data byte
to wiper change
MIN
TYP
(NOTE 1)
MAX
1
UNIT
µs
SERIAL INTERFACE SPECS
V
IL
V
IH
Hysteresis
(Note 8)
V
OL
(Note 8)
Cpin
(Note 8)
f
SCL
t
IN
(Note 8)
t
AA
(Note 8)
t
BUF
(Note 8)
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
A1, A0, SDA, and SCL input buffer
LOW voltage
A1, A0, SDA, and SCL input buffer
HIGH voltage
SDA and SCL input buffer hysteresis
SDA output buffer LOW voltage,
sinking 4mA
A1, A0, SDA, and SCL pin
capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
Input data setup time
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
Measured at the 30% of V
CC
crossing
Measured at the 70% of V
CC
crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
CC
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
From 30% to 70% of V
CC
From 70% to 30% of V
CC
Total on-chip and off-chip
1300
-0.3
0.7*V
CC
0.05*
V
CC
0
0.4
10
400
50
900
0.3*V
CC
V
CC
+0.3
V
V
V
V
pF
kHz
ns
ns
ns
1300
600
600
600
100
ns
ns
ns
ns
ns
t
HD:DAT
Input data hold time
0
ns
t
SU:STO
t
HD:STO
t
DH
(Note 8)
t
R
(Note 8)
t
F
(Note 8)
STOP condition hold time
STOP condition hold time for read, or
volatile only write
Output data hold time
600
600
0
ns
ns
ns
SDA and SCL rise time
SDA and SCL fall time
20 +
0.1 * Cb
20 +
0.1 * Cb
10
1
250
250
400
ns
ns
pF
k
Cb (Note 8) Capacitive loading of SDA or SCL
Rpu
(Note 8)
SDA and SCL bus pull-up resistor off- Maximum is determined by t
R
and t
F
chip
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
FN8096 Rev 1.00
January 16, 2006
Page 4 of 10
ISL90842
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
t
SU:A
t
HD:A
PARAMETER
A1 and A0 setup time
A1 and A0 hold time
TEST CONDITIONS
Before START condition
After STOP condition
MIN
600
600
TYP
(NOTE 1)
MAX
UNIT
ns
ns
SDA vs SCL Timing
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
SDA
(INPUT TIMING)
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STA
t
AA
SDA
(OUTPUT TIMING)
t
DH
t
BUF
A0 and A1 Pin Timing
START
SCL
CLK 1
STOP
SDA IN
t
SU:A
A0, A1
t
HD:A
NOTES:
1. Typical values are for T
A
= 25°C and 3.3V supply voltage.
2. MI =
|
R
255
– R
0
|
/ 255. R
255
and R
0
are the measured resistances for the DCP register set to FF hex and 00 hex, respectively.
3. Roffset = R
255
/ MI, when measuring between R
W
and R
H
.
4. RDNL = (R
i
– R
i-1
) / MI, for i = 32 to 255.
5. RINL = [R
i
– (MI • i) – R
0
] / MI, for i = 32 to 255.
6. R
MATCH
= (R
i,x
– R
i,y
)
/ MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
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