GS8321ZV18/32/36E-250/225/200/166/150/133
165-Bump FP-BGA
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 165-bump FP-BGA package
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz
1.8 V V
DD
1.8 V I/O
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8321ZV18/32/36E may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8321ZV18/32/36E is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 165-bump FP-BGA package.
Functional Description
The GS8321ZV18/32/36E is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
285
350
6.5
6.5
205
235
265
320
7.0
7.0
195
225
245
295
7.5
7.5
185
210
220 210 185 mA
260 240 215 mA
8.0 8.5 8.5 ns
8.0 8.5 8.5 ns
175 165 155 mA
200 190 175 mA
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03 11/2004
1/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8321ZV18/32/36E-250/225/200/166/150/133
GS8321ZV18/32/36E 165-Bump BGA Pin Description
Symbol
A
0
, A
1
An
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
CK
CKE
W
E
1
E
3
E
2
FT
G
ADV
ZZ
LBO
TMS
TDI
TDO
TCK
MCH
V
DD
V
SS
V
DDQ
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Flow Through / Pipeline Mode Control
Output Enable; active low
Burst address counter advance enable; active high
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.03 11/2004
5/31
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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