ISL6113, ISL6114
Dual Slot PCI-E Hot Plug Controllers
RODUCT
OBSOLETE P
PLACEMENT
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NO RECO
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contact ou
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1-888-IN
DATASHEET
FN6457
Rev 0.00
September 25, 2007
The ISL6113, ISL6114 both target the PCI-Express Add-in card
hot swap application. Together with a pair of N-Channel and
P-Channel MOSFETs, and two sense resistors per slot, either
provides compliant hot plug power control to any combination
of two PCI-Express X1, X4, X8 or X16 slots.
The ISL6113, ISL6114 feature a programmable current
regulated (CR) maximum level for a programmable period to
each voltage load so that both fault isolation protection and
imperviousness to electrical transients are provided.
For each +12V supply, the CR level is set by a resistor value
depending on the needs of the PCI-Express connector (X1, X4,
X8 or X16) to be powered. This resistor is a sub-ohm standard
value current sense resistor one for each slot and the voltage
across this resistor is compared to a 50mV reference providing
a nominal CR protection level adequately above the specific
slot maximum limits. The 3.3V supply uses a 15m sense
resistor compared to a 50mV reference to provide 3.3A of
maximum regulated current to all connector sizes. The
3.3VAUX is internally monitored and controlled to provide a
nominal maximum of 1A of AUX output current.
The CR period for each slot is set by a separate external
capacitor on the associated CFILTER pin. Once the CR period
has expired, the IC then quickly turns off its associated FETs
thus unloading the faulted card from the supply voltage rails. A
nominal 3.3V must always be present on the AUXI pin for
proper IC bias; this should be the 3.3VAUX supply if used, if not
the AUXI pin is tied directly to the 3VMAIN supply. Both ICs
employ a card presence detection input that disables the MAIN
and AUX enabling inputs if it is not pulled low. Output voltage
monitoring with both PCI-E Reset Not and Power Good Not
reporting along with OC Fault reporting are provided. Whereas
the ISL6113 has the same GATE drive and response
characteristics as the ISL6112, the ISL6114 has a lower turn-on
GATE drive current allowing for the use of smaller
compensation capacitors and thus much faster response to
Way Overcurrent (WOC) conditions. Additionally, the ISL6114
does not turn-on with the CR feature invoked as do the
ISL6112, ISL6113 allowing for shorter CR programmed
periods.The ISL6113, ISL6114 are footprint compatible for all
common pins, but not entirely function compatible with the
ISL6112’s QFN package as there are I/O differences.
Features
• Dual PCI-E Slot Hot Swap Power Control and Distribution
• Highest Accuracy External R
SENSE
Current Monitoring
On Main Supplies
• Programmable Current Regulation Protection Function for
X1, X4, X8, X16 Connectors
• Programmable Current Regulation Duration
• Programmable In-rush Protection During Turn-On
• Latch-off or Retry Modes After Failure
• Pb-free (RoHS Compliant)
Applications
• PCI-Express Servers
• Power Supply Distribution and Control
• Hot Swap/Electronic Breaker Circuits
• Network Hubs, Routers, Switches
• Hot Swap Bays, Cards and Modules
IF 3.3VAUX NOT
IMPLEMENTED
12VINA 12VSENSEA 12VOUTA 3VINA 3VSENSEA 3VOUTA
12VGATEA
3VGATEA
VSTBYA
VAUXA
PRSNTB
FAULTA
PRSNTA
PWRGDA
FORONA
PERSTA
FORONB
GPO_A0
AUXENA
ISL6113, ISL6114
ONA
GPO_B0
AUXENB
PERSTB
ONB
PWRGDB
GPI_A0
FAULTB
GPI_BO
VAUXB
CFILTERA
CFILTERB
GND
12VGATEB
3VGATEB
VSTBYB
12VINB 12VSENSEB 12VOUTB 3VINB 3SENSEB
3VOUTB
IF 3.3VAUX NOT
IMPLEMENTED
FIGURE 1. TYPICAL ISL6113, ISL6114 BLOCK DIAGRAM
APPLICATION IMPLEMENTATION
FN6457 Rev 0.00
September 25, 2007
Page 1 of 24
ISL6113, ISL6114
Ordering Information
PART
NUMBER
ISL6113IRZA
ISL6113IRZA-T*
ISL6114IRZA
ISL6114IRZA-T*
ISL6113EVAL1Z
ISL6114EVAL1Z
PART
MARKING
ISL6113 IRZ
ISL6113 IRZ
ISL6114 IRZ
ISL6114 IRZ
ISL6113 Evaluation Platform
ISL6114 Evaluation Platform
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
48 Ld 7x7 QFN
48 Ld 7x7 QFN Tape and Reel
48 Ld 7x7 QFN
48 Ld 7x7 QFN Tape and Reel
PACKAGE
(Pb-free)
PKG. DWG. #
L48.7x7
L48.7x7
L48.7x7
L48.7x7
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinout
ISL6113, ISL6114
(48 LD QFN)
TOP VIEW
AUXENA
AUXENB
PRSNTB
GPO_A0
GPO_B0
PRSNTA
GPI_B0
38
PERSTA
37
36 FAULTB
35 CFILTERB
34 12VGATEB
33 GND
GND
(EXPOSED BOTTOM PAD)
GND
(Exposed bottom pad)
32 12VINB
31 PWRGDB
30 NC
29 12VSENSEB
28 FORCE_ONB
27 12VOUTB
26 VSTBYB
25 3VINB
13
3VSENSEA
14
3VGATEA
15
VAUXA
16
3VOUTA
17
GND
18
PERSTB
19
NC
20
NC
21
3VOUTB
22
VAUXB
23
3VGATEB
24
3VSENSEB
GND
ONA
ONB
48
FAULTA
CFILTERA
12VGATEA
GPI_A0
12VINA
PWRGDA
NC
12VSENSEA
FORCE_ONA
12VOUTA
VSTBYA
3VINA
1
2
3
4
5
6
7
8
9
10
11
12
47
46
45
44
43
42
41
L/R
40
39
FN6457 Rev 0.00
September 25, 2007
Page 2 of 24
ISL6113, ISL6114
Functional Block Diagram (1 Channel)
ON
AUXEN
POWER-ON
RESET
250µs
VSTBY
UVLO
VAUX CHARGE
PUMP AND
MOSFET
12VSENSE
12VIN
3VSENSE
3VIN
50mV
ON/OFF
100mV*
ON/OFF
100mV*
3V
UVLO
ON/
OFF
LOGIC
12VPWRGD
12VOUT
CFILTER
1.25V
3VPWRGD
3VOUT
2.8V
VSTBY
INT
40k x 2
FORCE_ON
GPI
GPO
BOTH A AND B SLOTS SHARE THE L/R PIN.
L/R
PRSNT
GND
10.5V
VAUX
PWRGD
PWRGD
THERMAL
SHUTDOWN
ON/OFF
PERST
50mV
12V
UVLO
ON/OFF
VAUX
OVERCURRENT
3VIN
3VGATE
12V BIAS
FAULT
VSTBY
12VIN
12VGATE
VAUX
VSTBY
IREF
FN6457 Rev 0.00
September 25, 2007
Page 3 of 24
ISL6113, ISL6114
Pin Descriptions
PIN
9, 28
NAME
FORCE_ONA,
FORCE_ONB
FUNCTION
Asserting a FORCE_ON input low will turn on the MAIN and AUX supplies to the respective slot in a forced mode
over riding the ON input and the UV, OC and short circuit protections on those outputs. UVLO protection for the
VSTBY input is not affected by the FORCE_ON pins. Asserting FORCE_ON will cause the PWRGD and FAULT
outputs to enter their open-drain state. This input is internally pulled high to the VAUX rail. Functionality is disabled
when PRSNT is high.
Enable input for MAIN outputs use to enable or disable MAIN voltage supply (12V and 3.3V) outputs. Taking ONX
low after a fault resets the respective slots Main Output Fault Latch. Functionality is disabled when PRSNT is high.
44, 43
45, 42
5, 32
ONA, ONB
AUXENA, AUXENB 3.3VAUX Enable Input, enables the respective VAUX output. Pulling AUXENX low after a fault resets the
associated slot’s VAUX fault latch. Functionality is disabled when PRSNT is high.
12VINA,12VINB
Connect to 12VMAIN supply and high side of sense resistor. This is one of two pins for Kelvin connection to
measure the 50mV CR Vth. An undervoltage lockout prevents the IC main supply function until 12VIN >10V. The
current regulation threshold is set by connecting a sense resistor between this pin and 12VSENSE. When the
current-limit threshold of IR = 50mV is reached, the 12VGATE pin is modulated to maintain a constant 50mV
voltage across the sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is
maintained for CR duration, the circuit breaker is tripped and both GATE pins for the affected slot turn off the
switch FETs and thus turn off the supplies to the slot.
12V current sense low side input. This is the second of two pins for Kelvin connection to the R
SENSE
to measure
the 50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and
associated 12VIN pin.
12V output voltage monitor for UV condition. This is the voltage input downstream of the MOSFET that is delivered
to the add-in card load.
Connect to 3VMAIN supply and high side of sense resistor. This provides one of two pins for Kelvin connection to
measure the 50mV CR Vth. Undervoltage lockout (UVLO) prevents turn-on until 3VIN >2.75V. The current
regulation threshold is set by connecting a sense resistor between this pin and 3VSENSE. When the current-limit
threshold of IR = 50mV is reached, the 3VGATE pin is modulated to maintain a constant 50mV voltage across the
sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is maintained for the
CR duration, the circuit breaker is tripped and both FETs for the affected slot are turned-off.
3.3V current sense low side input. This provides the second of two pins for Kelvin connection for measuring the
50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and associated
3VINX pin.
3.3V output voltage monitor for UV condition. This is the voltage downstream of the MOSFET that is delivered to
the add-in card load.
An open drain output which is pulled low whenever the CR duration has expired due to an OC fault condition on
any of the MAIN or the AUX supplies or in the event of an IC over-temperature condition. If fault latch is invoked
by a MAIN (+12V, +3.3V) supply fault, then it is reset by pulling the faulted slot’s ON pin low. if fault was asserted
because of an OC fault condition on the slot’s AUX output then pulling the AUXEN input low will reset the latch.
Both enabling inputs must be pulled low to clear a fault condition on both the MAIN and VAUX outputs of the same
slot. Internal over-temperature limit is ~+140°C with a +20°C hysteresis.
3.3VAUX output to the PCI-E slot: This output connects to the VAUX pin of the PCI-E connector through an internal
0.3 FET. This output is current regulated to ~1A.
3.3V bias input for the IC, and internal VAUX switches. V
VSTBY
must always be present for proper IC bias, either
from a dedicated 3.3V or 3VMAIN if AUX supply not implemented.
Latch-off or Retry bar input. Tying this input low invokes a periodic retry to turn-on after current regulation timer
has expired on both slots. Leaving this pin open provides a latch-off operational mode after CR period has expired.
In this mode turn-on is initiated by cycling the appropriate EN input(s). This pin is internally pulled up to VSTBY.
The card presence detection input disables the operation of the FORCE_ON, ON and AUXEN inputs if not pulled
to GND. If after turn-on, the PRSNT input goes high then all associated outputs (MAIN and AUX) are turned off
immediately.
A POWER GOOD NOT signal that is asserted low while all output voltages are compliant.
~5ms debounced user attention input, driven by either a mechanical switch or digital signal form higher level
controller.
User attention output, that can be used to drive LEDs, alarms or other attention getting devices. Open drain with
90mA pull-down capability.
8, 29
12VSENSEA,
12VSENSEB
12VOUTA,
12VOUTB
3VINA, 3VINB
10, 27
12, 25
13, 24
3VSENSEA,
3VSENSEB
3VOUTA,
3VOUTB
FAULTA, FAULTB
16, 21
1, 36
15, 22
11, 26
41
VAUXA, VAUXB
VSTBYA
VSTBYB
L/R
40, 39
PRSNTA, PRSNTB
6, 31
4, 38
48, 47
PWRGDA,
PWRGDB
GPI_A0, GPI_B0
GPO_A0, GPO_B0
FN6457 Rev 0.00
September 25, 2007
Page 4 of 24
ISL6113, ISL6114
Pin Descriptions
(Continued)
PIN
3, 34
NAME
12VGATEA,
12VGATEB
FUNCTION
12VMAIN gate drive output, connects to gate of an external P-Channel MOSFET. During power-up, this pin is
pulled down with a 25µA (5µA for ISL6114) current to control the dv/dt ramp of the output voltage to the slot. During
CR, the voltage on this pin is modulated to maintain a constant current into the load. During power-down or
latch-off for an overcurrent fault, this pin is pulled high to 12VIN by internal sources.
3VMAIN gate drive outputs connects to gate of an external N-Channel MOSFET. During power-up this pin charges
up with a 25µA (5µA for ISL6114) current to control the dv/dt ramp of the output voltage to the slot load. During
CRTIM the voltage on this pin is modulated to maintain a constant current into the load. During power-down or
latch-off for an overcurrent fault this pin is pulled low by internal sources.
100ms delayed report of MAIN supplies output voltage compliance.
A capacitor connected between each of these pins and ground sets the current regulated duration (tFILTER) for
each slot. tFILTER is the amount of time for which a slot remains in current limit before its circuit breaker is tripped.
IC ground reference
No Connect
14,
23
3VGATEA,
3VGATEB
37, 18
2, 35
17, 33,
46
7,19, 20,
30
PERSTA,
PERSTB
CFILTERA,
CFILTERB
GND
NC
FN6457 Rev 0.00
September 25, 2007
Page 5 of 24
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