BUK9217-75B
N-channel TrenchMOS logic level FET
Rev. 02 — 3 February 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 185 °C rating
1.3 Applications
12 V, 24 V and 42 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
Conditions
T
j
≥
25 °C; T
j
≤
185 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
Min
-
-
-
-
-
Typ
-
-
-
Max Unit
75
64
167
V
A
W
mΩ
mΩ
total power dissipation T
mb
= 25 °C; see
Figure 2
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 10;
see
Figure 11
I
D
= 64 A; V
sup
≤
75 V;
R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25 °C; unclamped
V
GS
= 5 V; I
D
= 25 A; V
DS
= 60 V;
T
j
= 25 °C; see
Figure 12
Static characteristics
13.4 15
14.4 17
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
gate-drain charge
-
-
147
mJ
Dynamic characteristics
Q
GD
-
14
-
nC
Nexperia
BUK9217-75B
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
SOT428 (DPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9217-75B
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
Type number
BUK9217-75B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 3 February 2011
2 of 16
Nexperia
BUK9217-75B
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 64 A; V
sup
≤
75 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
185 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-55
-55
-
-
-
Max
75
75
15
64
45
256
167
185
185
64
256
147
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
75
I
D
(A)
50
03no50
120
P
der
(%)
80
03no96
25
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
200
T
mb
(°C)
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
BUK9217-75B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 3 February 2011
3 of 16
Nexperia
BUK9217-75B
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
100
µs
10
DC
1 ms
10 ms
100 ms
Limit R
DSon
= V
DS
/ I
D
t
p
= 10
µs
03no49
1
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9217-75B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 3 February 2011
4 of 16
Nexperia
BUK9217-75B
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
Conditions
Min
-
-
Typ
-
71.4
Max
0.95
-
Unit
K/W
K/W
thermal resistance from junction to mounting see
Figure 4
base
thermal resistance from junction to ambient
1
δ
= 0.5
Z
th(j-mb)
(K/W)
10
−1
0.2
0.1
0.05
0.02
03nk52
10
−2
single shot
P
δ
=
t
p
T
t
p
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9217-75B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 3 February 2011
5 of 16
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