DATASHEET
QUAD PLL WITH VCXO FOR HDTV
Description
The ICS477-05 generates five high-quality,
high-frequency clock outputs including two reference
outputs from a low frequency pullable crystal. It is
designed to replace crystals and crystal oscillators in
most electronic systems.
Using Phase-Locked-Loop (PLL) techniques, the
device runs from a fundamental mode, pullable crystal.
It can replace multiple crystals and oscillators, saving
board space and cost.
ICS477-05
Features
•
Packaged in 28-pin SSOP (QSOP)
•
Available in Pb-free packaging
•
Replaces a VCXO plus multiple crystals and
oscillators
•
On-chip patented VCXO pull range 200 ppm
(minimum)
•
•
•
•
•
•
Duty cycle of 45/55
Operating voltage of 3.3V
Advanced, low power, CMOS process
Input crystal frequency of 27 MHz
Five output clocks
Industrial temperature range available
Block Diagram
VDD
6
VIN
27 MHz
Pullable
Crystal
X1
Voltage
Controlled
Crystal
Oscillator
PLLA
Divide
Logic
and
Output
Enable
Control
54.054M
PLLB
PLLC
PLLD
74.175M
X2
External capacitors
may be required
54M
2
27M
10
PDTS
GND
IDT™ / ICS™
QUAD PLL WITH VCXO FOR HDTV
1
ICS477-05
REV H 062404
ICS477-05
QUAD PLL WITH VCXO FOR HDTV
VCXO AND SYNTHESIZER
Pin Assignment
X1
GND
GND
V IN
VDD
VDD
GND
GND
GND
GND
5 4 .0 5 4 M
NC
NC
7 4 .1 7 5 M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X2
VDD
PDTS
GND
VDD
VDD
VDD
GND
GND
GND
54M
NC
27M
27M
2 8 p in (1 5 0 m il) S S O P
Pin Descriptions
Pin
Number
1
2
3
4
5, 6, 22, 23,
24, 27
7, 8, 9, 10, 19,
20, 21
11
12, 13, 17
14
15, 16
18
25
26
28
Pin
Name
XI
GND
GND
VIN
VDD
GND
54.054M
NC
74.175M
27M
54M
GND
PDTS
X2
Pin Type
Input
Power
Power
Input
Power
Power
Output
-
Output
Output
Output
Power
Input
Input
Pin Description
Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.
Connect to ground.
Connect to ground.
VCXO Voltage input. Zero to 3.3 V analog control voltage for VCXO.
Connect to +3.3 V.
Connect to ground.
54.054 MHz clock output. Weak internal pull-down when tri-state.
No connect. Do not connect anything to these pins.
74.175 MHz clock output. Weak internal pull-down when tri-state.
27 MHz reference clock output. Weak internal pull-down when tri-state.
54 MHz clock output. Weak internal pull-down when tri-state.
Connect to ground.
Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
Crystal connection. Connect to a 27 MHz fundamental mode pullable crystal.
IDT™ / ICS™
QUAD PLL WITH VCXO FOR HDTV
2
ICS477-05
REV H 062404
ICS477-05
QUAD PLL WITH VCXO FOR HDTV
VCXO AND SYNTHESIZER
External Components
The ICS477-05 requires a minimum number of external
components for proper operation.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on
the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your
final layout, a frequency counter capable of about 1 ppm
resolution and accuracy, two power supplies, and some
samples of the crystals which you plan to use in
production, along with measured initial accuracy for
each crystal at the specified crystal load capacitance,
CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS477-05 to 3.3 V. Connect pin
4 of the ICS477-05 to the second power supply. Adjust
the voltage on pin 3 to 0V. Measure and record the
frequency of the 27 MHz output.
2. Adjust the voltage on pin 4 to 3.3 V. Measure and
record the frequency of the same output.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as
possible. For optimum device performance, the
decoupling capacitors should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω
.
Quartz Crystal
The ICS477-05 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS477-05 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS477-05 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS477-05. There should be no via’s
between the crystal pins and the X1 and X2 device pins.
There should be no signal traces underneath or close to
the crystal.
See application note MAN05 for complete crystal
specifications.
To calculate the centering error:
6
(
f
3.0V
–
f
t arg et
)
+
(
f
0V
–
f
t arg et
)
Error = 10 x ------------------------------------------------------------------------------
–
error
xtal
f
t arg et
Where:
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more than
25 ppm negative, the PC board has excessive stray
capacitance and a new PCB layout should be
IDT™ / ICS™
QUAD PLL WITH VCXO FOR HDTV
3
ICS477-05
REV H 062404
ICS477-05
QUAD PLL WITH VCXO FOR HDTV
VCXO AND SYNTHESIZER
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25 ppm).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS477-05. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS477-05. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125° C
260° C
IDT™ / ICS™
QUAD PLL WITH VCXO FOR HDTV
4
ICS477-05
REV H 062404
ICS477-05
QUAD PLL WITH VCXO FOR HDTV
VCXO AND SYNTHESIZER
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.15
Typ.
+3.3
Max.
+85
+3.45
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Supply Current
Power Down Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance, inputs
Nominal Output Impedance
Internal Pull-up Resistor
Internal Pull-down Resistor
Symbol
VDD
IDD
IDDPD
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
C
IN
Z
OUT
R
PUP
R
PD
Conditions
No load
No load
PDTS pin
PDTS pin
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12 mA
CLK output
Min.
3.15
Typ.
3.3
48
0.5
Max.
3.45
Units
V
mA
mA
V
2
0.8
VDD-0.4
2.4
0.4
±80
5
20
V
V
V
V
mA
pF
Ω
kΩ
kΩ
PDTS pin
CLK outputs
360
510
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Crystal Pullability
VCXO Gain
Output Rise Time
Output Fall Time
Clock Stabilization Time after
Power-up
Cycle Jitter (short term jitter)
Symbol
f
in
F
P
K
0
t
OR
t
OF
Conditions
Crystal input, Note 2
0V< VIN < 3.3 V
VIN = VDD/2 + 1 V
20% to 80%, Note 1
80% to 20%, Note 1
Min.
±100
Typ.
27
150
1.2
1.0
Max. Units
MHz
ppm
ppm/V
ns
ns
10
ms
ps
t
ja
±200
IDT™ / ICS™
QUAD PLL WITH VCXO FOR HDTV
5
ICS477-05
REV H 062404
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